Efficient Aging-aware Failure Probability Estimation Using Augmented Reliability and Subset Simulation

A circuit-aging simulation that efficiently calculates temporal change of rare circuit-failure probability is proposed. While conventional methods required a long computational time due to the necessity of conducting separate calculations of failure probability at each device age, the proposed Monte Carlo based method requires to run only a single set of simulation. By applying the augmented reliability and subset simulation framework, the change of failure probability along the lifetime of the device can be evaluated through the analysis of the Monte Carlo samples. Combined with the two-step sample generation technique, the proposed method reduces the computational time to about 1/6 of that of the conventional method while maintaining a sufficient estimation accuracy

Efficient Estimation of Reliability Metrics for Circuits in Deca-Nanometer Nodes

51 σ.Καθώς η τεχνολογία οδηγεί στη κατασκευή τρανζίστορ ολοένα και μικρότερων διαστάσεων, έχουν εμφανιστεί αρκετά φαινόμενα που επηρεάζουν την αξιοπιστία των ολοκληρωμένων κυκλωμάτων. Ένα από αυτά τα φαινόμενα ονομάζεται "Bias Temperature Instability", αποτελεί σημαντικό κίνδυνο για την αξιοπιστία των ολοκληρωμένων κυκλωμάτων και έχει παρατηρηθεί εδώ και πάνω από 30 χρόνια. Το πρώτο μοντέλο που προσπάθησε να εξηγήσει αυτό το φαινόμενο εμφανίστηκε πριν από 30 περίπου χρόνια, βασίστηκε στη διάχυση υδρογόνου και ως εκ τούτου ονομάστηκε "Reaction-Diffusion model". Πριν από μερικά χρόνια δημιουργήθηκε ένα νέο ατομιστικό μοντέλο το οποίο βασίζεται κυρίως στην εμφάνιση ελαττωμάτων στο διηλεκτρικό μεταξύ της πύλης και του καναλιού των FET τρανζίστορ. Μελετώντας κανείς τη βιβλιογραφία που αφορά στο ατομιστικό αυτό μοντέλο, μπορεί να συναντήσει εργαλεία που προσομοιώνουν με ακρίβεια το μοντέλο αλλά δυστυχώς απαιτούν αρκετό χρόνο για να εκτελεστούν, κάτι το οποίο τα καθιστά απαγορευτικά για εκτενή χρήση. Παράλληλα, υπάρχουν εργαλεία βασισμένα στο μοντέλο της διάχυσης τα οποία βέβαια αδυνατούν να παράξουν σωστά και λεπτομερή αποτελέσματα, κυρίως σε τεχνολογίες μικρών διαστάσεων. Η παρούσα λοιπόν διπλωματική εργασία παρουσιάζει τα αποτελέσματα ενός νέου και καινοτόμου εργαλείου το οποίο βασίζεται στο ατομιστικό μοντέλο, ωστόσο προσομοιώνει αποδοτικά αλλά και με ακρίβεια το φαινόμενο της γήρανσης. Ένα αντιπροσωπευτικό μονοπάτι στατικής μνήμης (SRAM) θα χρησιμοποιηθεί ως παράδειγμα της λειτουργίας του μοντέλου ενώ παράλληλα θα υπολογισθούν, με βάση τα αποτελέσματα των προσομοιώσεων αυτών, μετρικές, σημαντικές για το χαρακτηρισμό της απόδοσης και αξιοπιστίας του κυκλώματος, ενώ παράλληλα θα μελετηθούν λεπτομερώς και οι σχέσεις που τις συνδέουν.In modern technologies of integrated circuits (IC) and with the downscaling of device dimensions, various degradation modes constitute major reliability concerns. Bias Temperature Instability (BTI) is a representative example, posing as a significant reliability threat in Field-Effect Transistor (FET) technologies and has been known for more than 30 years. At first, the model that tried to explain this phenomenon was based on the Reaction-Diffusion (RD) theory and was developed nearly 30 years ago. Recently, an atomistic model has been proposed, that enables the modeling of BTI in modern technologies. By observing the amount of software designed to simulate the BTI degradation, tools can be found that are based on the atomistic theory but are computationally prohibitive when it comes to simulating complex circuits consisting of a large number of devices. Tools based on the RD model are unable to accurately capture the BTI-induced degradation, especially in devices with small dimensions. The current thesis is appropriately positioned since it discusses a novel simulation framework that is efficient yet highly accurate. A subset of an embedded Static Random Access Memory (SRAM) is used for verification purposes. The estimation of the functional yield of the circuit over three years of operation will be examined as well as other reliability metrics, such as defects per million (DPM), mean time to failure (MTTF) and failures in time (FIT rate). Finally, the interplay between these metrics is discussed and efficient computation methods are proposed for each one.Μιχαήλ Α. Νόλτση

Cross-Layer Resiliency Modeling and Optimization: A Device to Circuit Approach

The never ending demand for higher performance and lower power consumption pushes the VLSI industry to further scale the technology down. However, further downscaling of technology at nano-scale leads to major challenges. Reduced reliability is one of them, arising from multiple sources e.g. runtime variations, process variation, and transient errors. The objective of this thesis is to tackle unreliability with a cross layer approach from device up to circuit level

Identification and Rejuvenation of NBTI-Critical Logic Paths in Nanoscale Circuits

The Negative Bias Temperature Instability (NBTI) phenomenon is agreed to be one of the main reliability concerns in nanoscale circuits. It increases the threshold voltage of pMOS transistors, thus, slows down signal propagation along logic paths between flip-flops. NBTI may cause intermittent faults and, ultimately, the circuit’s permanent functional failures. In this paper, we propose an innovative NBTI mitigation approach by rejuvenating the nanoscale logic along NBTI-critical paths. The method is based on hierarchical identification of NBTI-critical paths and the generation of rejuvenation stimuli using an Evolutionary Algorithm. A new, fast, yet accurate model for computation of NBTI-induced delays at gate-level is developed. This model is based on intensive SPICE simulations of individual gates. The generated rejuvenation stimuli are used to drive those pMOS transistors to the recovery phase, which are the most critical for the NBTI-induced path delay. It is intended to apply the rejuvenation procedure to the circuit, as an execution overhead, periodically. Experimental results performed on a set of designs demonstrate reduction of NBTI-induced delays by up to two times with an execution overhead of 0.1 % or less. The proposed approach is aimed at extending the reliable lifetime of nanoelectronics

Control Strategies for Improving Reliability and Efficiency in Modular Power Converters

The significance of modular power converters has escalated drastically in various applications such as electrical energy distribution, industrial motor drives and More Electric Aircraft (MEA) owing to the benefits such as scalability, design flexibility, higher degree of fault tolerance and better maintenance. One of the main advantages of modular systems is the ability to replace the faulty converter cells during maintenance instead of the entire system. However, such maintenance cycles can result in a system of converter cells with different aging. A system with cells having different aging arises the threats of multiple maintenance, lower reliability and availability, and high maintenance costs. For controlling the thermal-stress based aging of modular power converters, power routing strategy was proposed. The thesis focuses on the different implementation strategies of power routing for modular converters. Power semiconductors are one of the most reliability critical components in power converters, and thermal-stress has been identified as the main cause of their failure. This thesis work concentrates on the power semiconductor reliability improvement algorithms. For improving system lifetime, virtual resistor based power routing algorithms for single stage and multi-stage modular architectures have been investigated through simulations and validated with experiment. A unified framework for routing the power in complex modular converter architectures is defined based on graph theory. Popular converter architectures for Smart Transformer (ST) and MEA applications are modeled as graphs to serve as the basis for developing power flow optimization. The effectiveness of graph theory for optimizing the power flow in modular systems is demonstrated with the help of proposed algorithms

Diseño de circuitos analógicos y de señal mixta con consideraciones de diseño físico y variabilidad

Advances in microelectronic technology has been based on an increasing capacity to integrate transistors, moving this industry to the nanoelectronics realm in recent years. Moore’s Law [1] has predicted (and somehow governed) the growth of the capacity to integrate transistors in a single IC. Nevertheless, while this capacity has grown steadily, the increasing number of design tasks that are involved in the creation of the integrated circuit and their complexity has led to a phenomenon known as the ``design gap´´. This is the difference between what can theoretically be integrated and what can practically be designed. Since the early 2000s, the International Technology Roadmap of Semiconductors (ITRS) reports, published by the Semiconductor Industry Association (SIA), alert about the necessity to limit the growth of the design cost by increasing the productivity of the designer to continue the semiconductor industry’s growth. Design automation arises as a key element to close this ”design gap”. In this sense, electronic design automation (EDA) tools have reached a level of maturity for digital circuits that is far behind the EDA tools that are made for analog circuit design automation. While digital circuits rely, in general, on two stable operation states (which brings inherent robustness against numerous imperfections and interferences, leading to few design constraints like area, speed or power consumption), analog signal processing, on the other hand, demands compliance with lots of constraints (e.g., matching, noise, robustness, ...). The triumph of digital CMOS circuits, thanks to their mentioned robustness, has, ultimately, facilitated the way that circuits can be processed by algorithms, abstraction levels and description languages, as well as how the design information traverse the hierarchical levels of a digital system. The field of analog design automation faces many more difficulties due to the many sources of perturbation, such as the well-know process variability, and the difficulty in treating these systematically, like digital tools can do. In this Thesis, different design flows are proposed, focusing on new design methodologies for analog circuits, thus, trying to close the ”gap” between digital and analog EDA tools. In this chapter, the most important sources for perturbations and their impact on the analog design process are discussed in Section 1.2. The traditional analog design flow is discussed in 1.3. Emerging design methodologies that try to reduce the ”design gap” are presented in Section 1.4 where the key concept of Pareto-Optimal Front (POF) is explained. This concept, brought from the field of economics, models the analog circuit performances into a set of solutions that show the optimal trade-offs among conflicting circuit performances (e.g. DC-gain and unity-gain frequency). Finally, the goals of this thesis are presented in Section 1.5

Prognostics and health management of power electronics

Prognostics and health management (PHM) is a major tool enabling systems to evaluate their reliability in real-time operation. Despite ground-breaking advances in most engineering and scientific disciplines during the past decades, reliability engineering has not seen significant breakthroughs or noticeable advances. Therefore, self-awareness of the embedded system is also often required in the sense that the system should be able to assess its own health state and failure records, and those of its main components, and take action appropriately. This thesis presents a radically new prognostics approach to reliable system design that will revolutionise complex power electronic systems with robust prognostics capability enhanced Insulated Gate Bipolar Transistors (IGBT) in applications where reliability is significantly challenging and critical. The IGBT is considered as one of the components that is mainly damaged in converters and experiences a number of failure mechanisms, such as bond wire lift off, die attached solder crack, loose gate control voltage, etc. The resulting effects mentioned are complex. For instance, solder crack growth results in increasing the IGBT’s thermal junction which becomes a source of heat turns to wire bond lift off. As a result, the indication of this failure can be seen often in increasing on-state resistance relating to the voltage drop between on-state collector-emitter. On the other hand, hot carrier injection is increased due to electrical stress. Additionally, IGBTs are components that mainly work under high stress, temperature and power consumptions due to the higher range of load that these devices need to switch. This accelerates the degradation mechanism in the power switches in discrete fashion till reaches failure state which fail after several hundred cycles. To this end, exploiting failure mechanism knowledge of IGBTs and identifying failure parameter indication are background information of developing failure model and prognostics algorithm to calculate remaining useful life (RUL) along with ±10% confidence bounds. A number of various prognostics models have been developed for forecasting time to failure of IGBTs and the performance of the presented estimation models has been evaluated based on two different evaluation metrics. The results show significant improvement in health monitoring capability for power switches.Furthermore, the reliability of the power switch was calculated and conducted to fully describe health state of the converter and reconfigure the control parameter using adaptive algorithm under degradation and load mission limitation. As a result, the life expectancy of devices has been increased. These all allow condition-monitoring facilities to minimise stress levels and predict future failure which greatly reduces the likelihood of power switch failures in the first place

Challenges and New Trends in Power Electronic Devices Reliability

The rapid increase in new power electronic devices and converters for electric transportation and smart grid technologies requires a deepanalysis of their component performances, considering all of the different environmental scenarios, overload conditions, and high stressoperations. Therefore, evaluation of the reliability and availability of these devices becomes fundamental both from technical and economicalpoints of view. The rapid evolution of technologies and the high reliability level offered by these components have shown that estimating reliability through the traditional approaches is difficult, as historical failure data and/or past observed scenarios demonstrate. With the aim topropose new approaches for the evaluation of reliability, in this book, eleven innovative contributions are collected, all focusedon the reliability assessment of power electronic devices and related components

Aging-Aware Design Methods for Reliable Analog Integrated Circuits using Operating Point-Dependent Degradation

The focus of this thesis is on the development and implementation of aging-aware design methods, which are suitable to satisfy current needs of analog circuit design. Based on the well known \gm/\ID sizing methodology, an innovative tool-assisted aging-aware design approach is proposed, which is able to estimate shifts in circuit characteristics using mostly hand calculation schemes. The developed concept of an operating point-dependent degradation leads to the definition of an aging-aware sensitivity, which is compared to currently available degradation simulation flows and proves to be efficient in the estimation of circuit degradation. Using the aging-aware sensitivity, several analog circuits are investigated and optimized towards higher reliability. Finally, results are presented for numerous target specifications

A static approach to investigate the impact of predictive maintenance in the reliability level and the failure cost of industrial installations

Digital IoT(Internet of Things)solutions for equipment condition monitoring andnew advanced algorithms to process big data, enablethe application of predictive maintenance.Consequently, actual implementations of such a system in industrial installations triggers theverification of its potentialbenefits. Thus, this project attempts to quantify the impact of a predictive maintenance system in the failure rate and the maintenance costof industrial installations.The lack oftime depended data lead to a static approach that utilizes average failure rate and mean time to repair values coming from IEEE standards and other sources. Next, a methodology that links the equipment causes of failure with a predictive maintenance system functions, is proposed. Consequently, new reduced failure rates for theassets under monitoring are defined.To perform the reliability calculations the spreadsheet methodology is presented and utilized. Additionally, the revenue requirement methodology is described and is used for the cost benefit analysis.Finally, the approach is applied in two theoretical and two actual industrial installations. Sensitivity analyses regarding different parameters of a predictive maintenance system are conducted in the first two cases,to evaluate the impact on different reliability indices. Moreover, cost benefit analysis is performed in the actual industrial networks and according to the resultspredictive maintenance should be preferred. Lastly, regarding the failure rate, a small or high reduction is observed depending on the type of failures, the utility sources,the system configuration,the number of monitored equipment and other paramet