343 research outputs found

    An investigation into 88 KV surge arrester failures in the Eskom east grid traction network

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    The Eskom East Grid Traction Network (EGTN) supplying traction loads and distribution networks has experienced at least one surge arrester failure over the past ten years. These failures results in poor network reliability and customer dissatisfactions which are often overlooked. This is because reliability indices used in the reliability evaluation of transmission and distribution networks are different. It is suspected that fast transient faults in this network initiate system faults leading to surge arrester design parameter exceedances and poor network insulation coordination. Preliminary investigations in network suggest that transient studies were not done during network planning and design stages. This may have resulted in the lack of surge arrester parameter evaluations under transient conditions leading to improper surge arresters being selected and installed in this network resulting in surge arrester failures that are now evident. These failures may also have been exacerbated by the dynamic nature of traction loads as they are highly unbalanced, have poor power factors and emit high voltage distortions. Poor in-service conditions such as defects, insulation partial discharges and overheating, bolted faults in the network and quality of supply emissions can also contribute to surge arrester failures. To address problems arising with different reliability indices in these networks the reliability of the EGTN is evaluated. In this work the reliability evaluation of the EGTN is done by computing common distribution reliability indices using analytic and simulation methods. This is done by applying the analytic method in the EGTN by assessing network failure modes and effects analysis (FMEA) when the surge arrester fails in this network. The simulation method is applied by applying and modifying the MATLAB code proposed by Shavuka et al. [1]. These reliability indices are then compared with transmission reliability indices over the same period. This attempts to standardize reliability evaluations in these networks. To assess the impact of transient faults in the surge arrester parameter evaluation the EGTN is modelled and simulated by initiating transient faults sequentially in the network at different nodes and under different loading conditions. This is done by using Power System Blockset (PSB), Power System Analysis Toolbox (PSAT) and Alternate Transient Program (ATP) simulation tools and computing important surge arrester parameters i.e. continuous operating voltage, rated voltage, discharge current and energy absorption capability (EAC). These parameters are assessed by in the EGTN by evaluating computed surge arrester parameters against parameters provided by manufacturers, the Eskom 88 kV surge arrester specification and those parameters recommended in IEC 60099-4. To assess the impact and contribution of in-service conditions, faults and quality of supply emissions in surge arrester failures these contributing factors are investigated by assessing infra-red scans, fault analysis reports, results of the sampled faulted surge arrester in this network and quality of supply parameters around the time of failures. This study found that Eskom transmission and distribution network reliability indices can be standardized as distribution reliability indices i.e. SAIDI, SAIFI, CAIDI, ASAI and ASUI indices are similar to Eskom transmission indices i.e. SM, NOI, circuit availability index and circuit unavailability index respectively. Transient simulations in this study showed that certain surge arresters in the EGTN had their rated surge arrester parameters exceeded under certain transient conditions and loading conditions. These surge arresters failed as their discharge currents and EACs were exceeded under heavy and light network loading conditions. This study concluded that surge arresters whose discharge currents and EACs exceeded were improperly evaluated and selected prior to their installations in the EGTN. This study found the EAC to be the most import parameter in surge arrester performance evaluations. The Eskom 88 kV surge arrester specification was found to be inadequate, inaccurate and ambiguous as a number of inconsistencies in the usage of IEEE and IEC classified systems terminology were found. It was concluded that these inconsistencies may have led to confusions for manufacturers during surge arrester designs and selections in the EGTN. The evaluation of fault reports showed that two surge arrester failures in this network were caused by hardware failures such as conductor failure and poor network operating as the line was continuously closed onto a fault. There was no evidence that poor in-service and quality of supply emissions contributed to surge arrester failures in this network. PSB, PSAT and ATP simulation tools were found adequate in modelling and simulating the EGTN. However the PSB tool was found to be slow as the network expanded and the PSAT required user defined surge arrester models requiring detailed manufacture data sheets which are not readily available. ATP was found to be superior in terms of speed and accuracy in comparison to the PSB and PSAT tools. The MATLAB code proposed by Shavuka et al. [1] was found to be suitable and accurate in assessing transmission networks as EGTN's reliability indices computed from this code were comparable to benchmarked Eskom distribution reliability indices. The work carried out in this research will assist in improving surge arrester performance evaluations, the current surge arrester specification and surge arrester selections. Simulation tools utilized in this work show great potential in achieving this. Reliability studies conducted in this work will assist in standardizing reliability indices between Eskom's transmission and distribution divisions. In-service condition assessment carried out in this work will improve surge arrester condition monitoring and preventive maintenance practices

    Data-Driven Query by Vocal Percussion

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    The imitation of percussive sounds via the human voice is a natural and effective tool for communicating rhythmic ideas on the fly. Query by Vocal Percussion (QVP) is a subfield in Music Information Retrieval (MIR) that explores techniques to query percussive sounds using vocal imitations as input, usually plosive consonant sounds. In this way, fully automated QVP systems can help artists prototype drum patterns in a comfortable and quick way, smoothing the creative workflow as a result. This project explores the potential usefulness of recent data-driven neural network models in two of the most important tasks in QVP. Algorithms relative to Vocal Percussion Transcription (VPT) detect and classify vocal percussion sound events in a beatbox-like performance so to trigger individual drum samples. Algorithms relative to Drum Sample Retrieval by Vocalisation (DSRV) use input vocal imitations to pick appropriate drum samples from a sound library via timbral similarity. Our experiments with several kinds of data-driven deep neural networks suggest that these achieve better results in both VPT and DSRV compared to traditional data-informed approaches based on heuristic audio features. We also find that these networks, when paired with strong regularisation techniques, can still outperform data-informed approaches when data is scarce. Finally, we gather several insights relative to people’s approach to vocal percussion and how user-based algorithms are essential to better model individual differences in vocalisation styles

    Methods and Results of Power Cycling Tests for Semiconductor Power Devices

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    This work intends to enhance the state of the research in power cycling tests with statements on achievable measurement accuracy, proposed test bench topologies and recommendations on improved test strategies for various types of semiconductor power devices. Chapters 1 and 2 describe the current state of the power cycling tests in the context of design for reliability comprising applicable standards and lifetime models. Measurement methods in power cycling tests for the essential physical parameters are explained in chapter 3. The dynamic and static measurement accuracy of voltage, current and temperature are discussed. The feasibly achievable measurement delay tmd of the maximal junction temperature Tjmax, its consequences on accuracy and methods to extrapolate to the time point of the turn-off event are explained. A method to characterize the thermal path of devices to the heatsink via measurements of the thermal impedance Zth is explained. Test bench topologies starting from standard setups, single to multi leg DC benches are discussed in chapter 4. Three application-closer setups implemented by the author are explained. For tests on thyristors a test concept with truncated sinusoidal current waveforms and online temperature measurement is introduced. An inverter-like topology with actively switching IGBTs is presented. In contrast to standard setups, there the devices under test prove switching capability until reaching the end-of-life criteria. Finally, a high frequency switching topology with low DC-link voltage and switching losses contributing significantly to the overall power losses is presented providing new degrees of freedom for setting test conditions. The particularities of semiconductor power devices in power cycling tests are thematized in chapter 5. The first part describes standard packages and addressed failure mechanisms in power cycling. For all relevant power electronic devices in silicon and silicon carbide, the devices’ characteristics, methods for power cycling and their consequences for test results are explained. The work is concluded and suggestions for future work are given in chapter 6.:Abstract 1 Kurzfassung 3 Acknowledgements 5 Nomenclature 10 Abbreviations 10 Symbols 12 1 Introduction 19 2 Applicable Standards and Lifetime Models 25 3 Measurement parameters in power cycling tests 53 4 Test Bench Topologies 121 5 Semiconductor Power Devices in Power Cycling 158 6 Conclusion and Outlook 229 References 235 List of Publications 253 Theses 257Diese Arbeit bereichert den Stand der Wissenschaft auf dem Gebiet von Lastwechseltests mit Beiträgen zu verbesserter Messgenauigkeit, vorgeschlagenen Teststandstopologien und verbesserten Teststrategien für verschiedene Arten von leistungselektronischen Bauelementen. Kurzgefasst der Methodik von Lastwechseltests. Das erste Themengebiet in Kapitel 1 und Kapitel 2 beschreibt den aktuellen Stand zu Lastwechseltests im Kontext von Design für Zuverlässigkeit, welcher in anzuwendenden Standards und publizierten Lebensdauermodellen dokumentiert ist. Messmethoden für relevante physikalische Parameter in Lastwechseltests sind in Kapitel 3. erläutert. Zunächst werden dynamische und statische Messgenauigkeit für Spannung, Strom und Temperaturen diskutiert. Die tatsächlich erreichbare Messverzögerung tMD der maximalen Sperrschichttemperatur Tjmax und deren Auswirkung auf die Messgenauigkeit der Lastwechselfestigkeit wird dargelegt. Danach werden Methoden zur Rückextrapolation zum Zeitpunkt des Abschaltvorgangs des Laststroms diskutiert. Schließlich wird die Charakterisierung des Wärmepfads vom Bauelement zur Wärmesenke mittels Messung der thermischen Impedanz Zth behandelt. In Kapitel 4 werden Teststandstopologien beginnend mit standardmäßig genutzten ein- und mehrsträngigen DC-Testständen vorgestellt. Drei vom Autor umgesetzte anwendungsnahe Topologien werden erklärt. Für Tests mit Thyristoren wird ein Testkonzept mit angeschnittenem sinusförmigem Strom und in situ Messung der Sperrschichttemperatur eingeführt. Eine umrichterähnliche Topologie mit aktiv schaltenden IGBTs wird vorgestellt. Zuletzt wird eine Topologie mit hoch frequent schaltenden Prüflingen an niedriger Gleichspannung bei der Schaltverluste signifikant zur Erwärmung der Prüflinge beitragen vorgestellt. Dies ermöglicht neue Freiheitsgrade um Testbedingungen zu wählen. Die Besonderheiten von leistungselektronischen Bauelementen werden in Kapitel 5 thematisiert. Der erste Teil beschreibt Gehäusetypen und adressierte Fehlermechanismen in Lastwechseltests. Für alle untersuchten Bauelementtypen in Silizium und Siliziumkarbid werden Charakteristiken, empfohlene Methoden für Lastwechseltests und Einflüsse auf Testergebnisse erklärt. Die Arbeit wird in Kapitel 6 zusammengefasst und Vorschläge zu künftigen Arbeiten werden unterbreitet.:Abstract 1 Kurzfassung 3 Acknowledgements 5 Nomenclature 10 Abbreviations 10 Symbols 12 1 Introduction 19 2 Applicable Standards and Lifetime Models 25 3 Measurement parameters in power cycling tests 53 4 Test Bench Topologies 121 5 Semiconductor Power Devices in Power Cycling 158 6 Conclusion and Outlook 229 References 235 List of Publications 253 Theses 25

    Formal Verification and Fault Mitigation for Small Avionics Platforms using Programmable Logic

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    As commercial and personal unmanned aircraft gain popularity and begin to account for more traffic in the sky, the reliability and integrity of their flight controllers becomes increasingly important. As these aircraft get larger and start operating over longer distances and at higher altitude they will start to interact with other controlled air traffic and the risk of a failure in the control system becomes much more severe. As any engineer who has investigated any space bound technology will know, digital systems do not always behave exactly as they are supposed to. This can be attributed to the effects of high energy particles in the atmosphere that can deposit energy randomly throughout a digital circuit. These single event effects are capable of producing transient logic levels and altering the state of registers in a circuit, corrupting data and possibly leading to a failure of the flight controller. These effects become more common as altitude increases, as well as with the increase of registers in a digital system. High integrity flight controllers also require more development effort to show that they meet the required standard. Formal methods can be used to verify digital systems and prove that they meet certain specifications. For traditional software systems that perform many tasks on shared computational resources, formal methods can be quite difficult if not impossible to implement. The use of discrete logic controllers in the form of FPGAs greatly simplifies multitasking by removing the need for shared resources. This simplicity allows formal methods to be applied during the development of the flight control algorithms & device drivers. In this thesis we propose and demonstrate a flight controller implemented entirely within an FPGA to investigate the differences and difficulties when compared with traditional CPU software implementations. We go further to provide examples of formal verifications of specific parts of the flight control firmware to demonstrate the ease with which this can be achieved. We also make efforts to protect the flight controller from the effects of radiation at higher altitudes using both passive hardware design and active register transfer level algorithms

    Design and Control of Power Converters 2019

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    In this book, 20 papers focused on different fields of power electronics are gathered. Approximately half of the papers are focused on different control issues and techniques, ranging from the computer-aided design of digital compensators to more specific approaches such as fuzzy or sliding control techniques. The rest of the papers are focused on the design of novel topologies. The fields in which these controls and topologies are applied are varied: MMCs, photovoltaic systems, supercapacitors and traction systems, LEDs, wireless power transfer, etc

    Design for Electromagnetic Compatibility--In a Nutshell

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    This open access book provides practicing electrical engineers and students a practical – and mathematically sound – introduction to the topic of electromagnetic compatibility (EMC). The author enables readers to understand better how to overcome commonly failed EMC tests for radiated emission, radiated immunity, and electrostatic discharge (ESD), while providing concrete EMC design guidelines. The book also presents an overview of EMC standards and regulations and how to test for a global market access

    Study and design of topologies and components for high power density DC-DC converters

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    Size reduction of low power electronic DC–DC converters is a topic of major interest for power electronics which requires the study and design of circuits and components working under redefined requirements. For this purpose, novel circuital topologies provide advantages in terms of power density increment, especially where a single chip design is feasible. These concepts have been applied to design and implement an integrated high step-down multiphase buck converter and to study the miniaturization of a stackable fiflyback architecture. Particular attention has been dedicated to power inductors, focusing on the modeling and measurement of magnetic materials’ hysteresis and core losses
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