821 research outputs found
EffiTest: Efficient Delay Test and Statistical Prediction for Configuring Post-silicon Tunable Buffers
At nanometer manufacturing technology nodes, process variations significantly
affect circuit performance. To combat them, post- silicon clock tuning buffers
can be deployed to balance timing bud- gets of critical paths for each
individual chip after manufacturing. The challenge of this method is that path
delays should be mea- sured for each chip to configure the tuning buffers
properly. Current methods for this delay measurement rely on path-wise
frequency stepping. This strategy, however, requires too much time from ex-
pensive testers. In this paper, we propose an efficient delay test framework
(EffiTest) to solve the post-silicon testing problem by aligning path delays
using the already-existing tuning buffers in the circuit. In addition, we only
test representative paths and the delays of other paths are estimated by
statistical delay prediction. Exper- imental results demonstrate that the
proposed method can reduce the number of frequency stepping iterations by more
than 94% with only a slight yield loss.Comment: ACM/IEEE Design Automation Conference (DAC), June 201
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Όλ¬Έ (λ°μ¬) -- μμΈλνκ΅ λνμ : 곡과λν μ κΈ°Β·μ 보곡νλΆ, 2020. 8. κΉνν.Timing analysis is one of the necessary steps in the development of a semiconductor circuit. In addition, it is increasingly important in the advanced process technologies due to various factors, including the increase of processβvoltageβtemperature variation. This dissertation addresses three problems related to timing analysis and optimization in logic and physical synthesis. Firstly, most static timing analysis today are based on conventional fixed flip-flop timing models, in which every flip-flop is assumed to have a fixed clock-to-Q delay. However, setup and hold skews affect the clock-to-Q delay in reality. In this dissertation, I propose a mathematical formulation to solve the problem and apply it to the clock skew scheduling problems as well as to the analysis of a given circuit, with a scalable speedup technique. Secondly, near-threshold computing is one of the promising concepts for energy-efficient operation of VLSI systems, but wide performance variation and nonlinearity to process variations block the proliferation. To cope with this, I propose a holistic hardware performance monitoring methodology for accurate timing prediction in a near-threshold voltage regime and advanced process technology. Lastly, an asynchronous circuit is one of the alternatives to the conventional synchronous style, and asynchronous pipeline circuit especially attractive because of its small design effort. This dissertation addresses the synthesis problem of lightening two-phase bundled-data asynchronous pipeline controllers, in which delay buffers are essential for guaranteeing the correct handshaking operation but incurs considerable area increase.νμ΄λ° λΆμμ λ°λ체 νλ‘ κ°λ° νμ κ³Όμ μ€ νλλ‘, μ΅μ 곡μ μΌμλ‘ κ³΅μ -μ μ-μ¨λ λ³μ΄ μ¦κ°λ₯Ό ν¬ν¨ν λ€μν μμΈμΌλ‘ νμ¬κΈ κ·Έ μ€μμ±μ΄ 컀μ§κ³ μλ€. λ³Έ λ
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λ λλ μ΄ λ²νΌμ μν λ©΄μ μ¦κ°λ₯Ό μνν μ μλ ν©μ± κΈ°λ²μ μ μνμλ€.1 INTRODUCTION 1
1.1 Flexible Flip-Flop Timing Model 1
1.2 Hardware Performance Monitoring Methodology 4
1.3 Asynchronous Pipeline Controller 10
1.4 Contributions of this Dissertation 15
2 ANALYSIS AND OPTIMIZATION CONSIDERING FLEXIBLE FLIP-FLOP TIMING MODEL 17
2.1 Preliminaries 17
2.1.1 Terminologies 17
2.1.2 Timing Analysis 20
2.1.3 Clock-to-Q Delay Surface Modeling 21
2.2 Clock-to-Q Delay Interval Analysis 22
2.2.1 Derivation 23
2.2.2 Additional Constraints 26
2.2.3 Analysis: Finding Minimum Clock Period 28
2.2.4 Optimization: Clock Skew Scheduling 30
2.2.5 Scalable Speedup Technique 33
2.3 Experimental Results 37
2.3.1 Application to Minimum Clock Period Finding 37
2.3.2 Application to Clock Skew Scheduling 39
2.3.3 Efficacy of Scalable Speedup Technique 43
2.4 Summary 44
3 HARDWARE PERFORMANCE MONITORING METHODOLOGY AT NTC AND ADVANCED TECHNOLOGY NODE 45
3.1 Overall Flow of Proposed HPM Methodology 45
3.2 Prerequisites to HPM Methodology 47
3.2.1 BEOL Process Variation Modeling 47
3.2.2 Surrogate Model Preparation 49
3.3 HPM Methodology: Design Phase 52
3.3.1 HPM2PV Model Construction 52
3.3.2 Optimization of Monitoring Circuits Configuration 54
3.3.3 PV2CPT Model Construction 58
3.4 HPM Methodology: Post-Silicon Phase 60
3.4.1 Transfer Learning in Silicon Characterization Step 60
3.4.2 Procedures in Volume Production Phase 61
3.5 Experimental Results 62
3.5.1 Experimental Setup 62
3.5.2 Exploration of Monitoring Circuits Configuration 64
3.5.3 Effectiveness of Monitoring Circuits Optimization 66
3.5.4 Considering BEOL PVs and Uncertainty Learning 68
3.5.5 Comparison among Different Prediction Flows 69
3.5.6 Effectiveness of Prediction Model Calibration 71
3.6 Summary 73
4 LIGHTENING ASYNCHRONOUS PIPELINE CONTROLLER 75
4.1 Preliminaries and State-of-the-Art Work 75
4.1.1 Bundled-data vs. Dual-rail Asynchronous Circuits 75
4.1.2 Two-phase vs. Four-phase Bundled-data Protocol 76
4.1.3 Conventional State-of-the-Art Pipeline Controller Template 77
4.2 Delay Path Sharing for Lightening Pipeline Controller Template 78
4.2.1 Synthesizing Sharable Delay Paths 78
4.2.2 Validating Logical Correctness for Sharable Delay Paths 80
4.2.3 Reformulating Timing Constraints of Controller Template 81
4.2.4 Minimally Allocating Delay Buffers 87
4.3 In-depth Pipeline Controller Template Synthesis with Delay Path Reusing 88
4.3.1 Synthesizing Delay Path Units 88
4.3.2 Validating Logical Correctness of Delay Path Units 89
4.3.3 Updating Timing Constraints for Delay Path Units 91
4.3.4 In-depth Synthesis Flow Utilizing Delay Path Units 95
4.4 Experimental Results 99
4.4.1 Environment Setup 99
4.4.2 Piecewise Linear Modeling of Delay Path Unit Area 99
4.4.3 Comparison of Power, Performance, and Area 102
4.5 Summary 107
5 CONCLUSION 109
5.1 Chapter 2 109
5.2 Chapter 3 110
5.3 Chapter 4 110
Abstract (In Korean) 127Docto
Algorithmic techniques for nanometer VLSI design and manufacturing closure
As Very Large Scale Integration (VLSI) technology moves to the nanoscale
regime, design and manufacturing closure becomes very difficult to achieve due to
increasing chip and power density. Imperfections due to process, voltage and temperature variations aggravate the problem. Uncertainty in electrical characteristic of
individual device and wire may cause significant performance deviations or even functional failures. These impose tremendous challenges to the continuation of Moore's
law as well as the growth of semiconductor industry.
Efforts are needed in both deterministic design stage and variation-aware design
stage. This research proposes various innovative algorithms to address both stages for
obtaining a design with high frequency, low power and high robustness. For deterministic optimizations, new buffer insertion and gate sizing techniques are proposed. For
variation-aware optimizations, new lithography-driven and post-silicon tuning-driven
design techniques are proposed.
For buffer insertion, a new slew buffering formulation is presented and is proved
to be NP-hard. Despite this, a highly efficient algorithm which runs > 90x faster
than the best alternatives is proposed. The algorithm is also extended to handle
continuous buffer locations and blockages.
For gate sizing, a new algorithm is proposed to handle discrete gate library in
contrast to unrealistic continuous gate library assumed by most existing algorithms. Our approach is a continuous solution guided dynamic programming approach, which
integrates the high solution quality of dynamic programming with the short runtime
of rounding continuous solution.
For lithography-driven optimization, the problem of cell placement considering
manufacturability is studied. Three algorithms are proposed to handle cell flipping
and relocation. They are based on dynamic programming and graph theoretic approaches, and can provide different tradeoff between variation reduction and wire-
length increase.
For post-silicon tuning-driven optimization, the problem of unified adaptivity
optimization on logical and clock signal tuning is studied, which enables us to significantly save resources. The new algorithm is based on a novel linear programming
formulation which is solved by an advanced robust linear programming technique.
The continuous solution is then discretized using binary search accelerated dynamic
programming, batch based optimization, and Latin Hypercube sampling based fast
simulation
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MANAGING AND LEVERAGING VARIATIONS AND NOISE IN NANOMETER CMOS
Advanced CMOS technologies have enabled high density designs at the cost of complex fabrication process. Variation in oxide thickness and Random Dopant Fluctuation (RDF) lead to variation in transistor threshold voltage Vth. Current photo-lithography process used for printing decreasing critical dimensions result in variation in transistor channel length and width. A related challenge in nanometer CMOS is that of on-chip random noise. With decreasing threshold voltage and operating voltage; and increasing operating temperature, CMOS devices are more sensitive to random on-chip noise in advanced technologies.
In this thesis, we explore novel circuit techniques to manage the impact of process variation in nanometer CMOS technologies. We also analyze the impact of on-chip noise on CMOS circuits and propose techniques to leverage or manage impact of noise based on the application. True Random Number Generator (TRNG) is an interesting cryptographic primitive that leverages on-chip noise to generate random bits; however, it is highly sensitive to process variation. We explore novel metastability circuits to alleviate the impact of variations and at the same time leverage on-chip noise sources like Random Thermal Noise and Random Telegraph Noise (RTN) to generate high quality random bits. We develop stochastic models for metastability based TRNG circuits to analyze the impact of variation and noise. The stochastic models are used to analyze and compare low power, energy efficient and lightweight post-processing techniques targeted to low power applications like System on Chip (SoC) and RFID. We also propose variation aware circuit calibration techniques to increase reliability. We extended this technique to a more generic application of designing Post-Si Tunable (PST) clock buffers to increase parametric yield in the presence of process variation. Apart from one time variation due to fabrication process, transistors undergo constant change in threshold voltage due to aging/wear-out effects and RTN. Process variation affects conventional sensors and introduces inaccuracies during measurement. We present a lightweight wear-out sensor that is tolerant to process variation and provides a fine grained wear-out sensing. A similar circuit is designed to sense fluctuation in transistor threshold voltage due to RTN. Although thermal noise and RTN are leveraged in applications like TRNG, they affect the stability of sensitive circuits like Static Random Access Memory (SRAM). We analyze the impact of on-chip noise on Bit Error Rate (BER) and post-Si test coverage of SRAM cells
Variability-Aware VLSI Design Automation For Nanoscale Technologies
As technology scaling enters the nanometer regime, design of large scale ICs gets more challenging due to shrinking feature sizes and increasing design complexity. Aggressive scaling causes significant degradation in reliability, increased susceptibility to fabrication and environmental randomness and increased dynamic and leakage power dissipation. In this work, we investigate these scaling issues in large scale integrated systems.
This dissertation proposes to develop variability-aware design methodologies by proposing design analysis, design-time optimization, post-silicon tunability and runtime-adaptivity based optimization techniques for handling variability. We discuss our research in the area of variability-aware analysis, specifically
focusing on the problem of statistical timing analysis. The first technique presents the concept of error budgeting that achieves significant runtime speedups during statistical timing analysis. The second work presents a general framework for non-linear non-Gaussian statistical timing analysis considering correlations.
Further, we present our work on design-time optimization schemes that are applicable during physical synthesis. Firstly, we present a buffer insertion technique that considers wire-length uncertainty and proposes algorithms to perform probabilistic buffer insertion. Secondly, we present a stochastic optimization framework
based on Monte-Carlo technique considering fabrication variability. This optimization framework can be applied to problems that can be modeled as linear programs without without imposing any assumptions on the nature of the variability.
Subsequently, we present our work on post-silicon tunability based design optimization. This work presents a design management framework that can be used to balance the effort spent on pre-silicon (through gate sizing) and post-silicon optimization (through tunable clock-tree buffers) while maximizing the yield gains. Lastly, we present our work on variability-aware runtime optimization techniques. We look at the problem of runtime supply voltage scaling for dynamic power optimization, and propose a framework to consider the impact of variability on the reliability of such designs. We propose a probabilistic design synthesis technique
where reliability of the design is a primary optimization metric
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TIME-DIFFERENCE CIRCUITS: METHODOLOGY, DESIGN, AND DIGITAL REALIZATION
This thesis presents innovations for a special class of circuits called Time Difference (TD) circuits. We introduce a signal processing methodology with TD signals that alters the target signal from a magnitude perspective to time interval between two time events and systematically organizes the primary TD functions abstracted from existing TD circuits and systems. The TD circuits draw attention from a broad range of application fields. In addition, highly evolved complementary metal-oxide-semiconductor (CMOS) technology suffers from various problems related to voltage and current amplitude signal processing methods. Compared to traditional analog and digital circuits, TD circuits bring several compelling features: high-resolution, high-throughput, and low-design complexity with digital integration capability. Further, the fabrication technology is advancing into the nanometer regime; the reduction in voltage headroom limits the performance of traditional analog/mixed-signal designs. All-digital design of time-difference circuit needs to be stressed to adapt to the low-cost, low-power, and high-portability applications.
We focus on Time-to-Digital Converters (TDC), one of the crucial building blocks in TD circuits. A novel algorithmic architecture is proposed based on a binary search algorithm and validated with both simulation and fabricated silicon. An all-digital structure Time-difference Amplifier (TDA) is designed and implemented to make FPGA and other all-digital implementations for TDC and related TD circuits feasible. Besides, we propose an all-digital timing measurement circuit based on the process variation from CMOS fabrication: PVTMC, which achieves a high measurement resolution:
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