496 research outputs found
An Implementation of List Successive Cancellation Decoder with Large List Size for Polar Codes
Polar codes are the first class of forward error correction (FEC) codes with
a provably capacity-achieving capability. Using list successive cancellation
decoding (LSCD) with a large list size, the error correction performance of
polar codes exceeds other well-known FEC codes. However, the hardware
complexity of LSCD rapidly increases with the list size, which incurs high
usage of the resources on the field programmable gate array (FPGA) and
significantly impedes the practical deployment of polar codes. To alleviate the
high complexity, in this paper, two low-complexity decoding schemes and the
corresponding architectures for LSCD targeting FPGA implementation are
proposed. The architecture is implemented in an Altera Stratix V FPGA.
Measurement results show that, even with a list size of 32, the architecture is
able to decode a codeword of 4096-bit polar code within 150 us, achieving a
throughput of 27MbpsComment: 4 pages, 4 figures, 4 tables, Published in 27th International
Conference on Field Programmable Logic and Applications (FPL), 201
On Path Memory in List Successive Cancellation Decoder of Polar Codes
Polar code is a breakthrough in coding theory. Using list successive
cancellation decoding with large list size L, polar codes can achieve excellent
error correction performance. The L partial decoded vectors are stored in the
path memory and updated according to the results of list management. In the
state-of-the-art designs, the memories are implemented with registers and a
large crossbar is used for copying the partial decoded vectors from one block
of memory to another during the update. The architectures are quite area-costly
when the code length and list size are large. To solve this problem, we propose
two optimization schemes for the path memory in this work. First, a folded path
memory architecture is presented to reduce the area cost. Second, we show a
scheme that the path memory can be totally removed from the architecture.
Experimental results show that these schemes effectively reduce the area of
path memory.Comment: 5 pages, 6 figures, 2 table
Comparison of Polar Decoders with Existing Low-Density Parity-Check and Turbo Decoders
Polar codes are a recently proposed family of provably capacity-achieving
error-correction codes that received a lot of attention. While their
theoretical properties render them interesting, their practicality compared to
other types of codes has not been thoroughly studied. Towards this end, in this
paper, we perform a comparison of polar decoders against LDPC and Turbo
decoders that are used in existing communications standards. More specifically,
we compare both the error-correction performance and the hardware efficiency of
the corresponding hardware implementations. This comparison enables us to
identify applications where polar codes are superior to existing
error-correction coding solutions as well as to determine the most promising
research direction in terms of the hardware implementation of polar decoders.Comment: Fixes small mistakes from the paper to appear in the proceedings of
IEEE WCNC 2017. Results were presented in the "Polar Coding in Wireless
Communications: Theory and Implementation" Worksho
A Multi-Kernel Multi-Code Polar Decoder Architecture
Polar codes have received increasing attention in the past decade, and have
been selected for the next generation of wireless communication standard. Most
research on polar codes has focused on codes constructed from a
polarization matrix, called binary kernel: codes constructed from binary
kernels have code lengths that are bound to powers of . A few recent works
have proposed construction methods based on multiple kernels of different
dimensions, not only binary ones, allowing code lengths different from powers
of . In this work, we design and implement the first multi-kernel successive
cancellation polar code decoder in literature. It can decode any code
constructed with binary and ternary kernels: the architecture, sized for a
maximum code length , is fully flexible in terms of code length, code
rate and kernel sequence. The decoder can achieve frequency of more than
GHz in nm CMOS technology, and a throughput of Mb/s. The area
occupation ranges between mm for and mm for
. Implementation results show an unprecedented degree of
flexibility: with , up to code lengths can be decoded with
the same hardware, along with any kernel sequence and code rate
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