A Reconfigurable Outer Modem Platform for Future Communications Systems

Future mobile and wireless communications networks require flexible modem architectures with high performance. Efficient utilization of application specific flexibility is key to fulfill these requirements. For high throughput a single processor can not provide the necessary computational power. Hence multi-processor architectures become necessary. This paper presents a multi-processor platform based on a new dynamically reconfigurable application specific instruction set processor (dr-ASIP) for the application domain of channel decoding. Inherently parallel decoding tasks can be mapped onto individual processing nodes. The implied challenging inter-processor communication is efficiently handled by a Network-on-Chip (NoC) such that the throughput of each node is not degraded. The dr-ASIP features Viterbi and Log-MAP decoding for support of convolutional and turbo codes of more than 10 currently specified mobile and wireless standards. Furthermore, its flexibility allows for adaptation to future systems

Comparison of Polar Decoders with Existing Low-Density Parity-Check and Turbo Decoders

Polar codes are a recently proposed family of provably capacity-achieving error-correction codes that received a lot of attention. While their theoretical properties render them interesting, their practicality compared to other types of codes has not been thoroughly studied. Towards this end, in this paper, we perform a comparison of polar decoders against LDPC and Turbo decoders that are used in existing communications standards. More specifically, we compare both the error-correction performance and the hardware efficiency of the corresponding hardware implementations. This comparison enables us to identify applications where polar codes are superior to existing error-correction coding solutions as well as to determine the most promising research direction in terms of the hardware implementation of polar decoders.Comment: Fixes small mistakes from the paper to appear in the proceedings of IEEE WCNC 2017. Results were presented in the "Polar Coding in Wireless Communications: Theory and Implementation" Worksho

On chip interconnects for multiprocessor turbo decoding architectures

International audienc

Self-concatenated code design and its application in power-efficient cooperative communications

In this tutorial, we have focused on the design of binary self-concatenated coding schemes with the help of EXtrinsic Information Transfer (EXIT) charts and Union bound analysis. The design methodology of future iteratively decoded self-concatenated aided cooperative communication schemes is presented. In doing so, we will identify the most important milestones in the area of channel coding, concatenated coding schemes and cooperative communication systems till date and suggest future research directions

On Complexity, Energy- and Implementation-Efficiency of Channel Decoders

Future wireless communication systems require efficient and flexible baseband receivers. Meaningful efficiency metrics are key for design space exploration to quantify the algorithmic and the implementation complexity of a receiver. Most of the current established efficiency metrics are based on counting operations, thus neglecting important issues like data and storage complexity. In this paper we introduce suitable energy and area efficiency metrics which resolve the afore-mentioned disadvantages. These are decoded information bit per energy and throughput per area unit. Efficiency metrics are assessed by various implementations of turbo decoders, LDPC decoders and convolutional decoders. New exploration methodologies are presented, which permit an appropriate benchmarking of implementation efficiency, communications performance, and flexibility trade-offs. These exploration methodologies are based on efficiency trajectories rather than a single snapshot metric as done in state-of-the-art approaches.Comment: Submitted to IEEE Transactions on Communication

Frequency Domain Hybrid-ARQ Chase Combining for Broadband MIMO CDMA Systems

In this paper, we consider high-speed wireless packet access using code division multiple access (CDMA) and multiple-input multiple-output (MIMO). Current wireless standards, such as high speed packet access (HSPA), have adopted multi-code transmission and hybrid-automatic repeat request (ARQ) as major technologies for delivering high data rates. The key technique in hybrid-ARQ, is that erroneous data packets are kept in the receiver to detect/decode retransmitted ones. This strategy is refereed to as packet combining. In CDMA MIMO-based wireless packet access, multi-code transmission suffers from severe performance degradation due to the loss of code orthogonality caused by both interchip interference (ICI) and co-antenna interference (CAI). This limitation results in large transmission delays when an ARQ mechanism is used in the link layer. In this paper, we investigate efficient minimum mean square error (MMSE) frequency domain equalization (FDE)-based iterative (turbo) packet combining for cyclic prefix (CP)-CDMA MIMO with Chase-type ARQ. We introduce two turbo packet combining schemes: i) In the first scheme, namely "chip-level turbo packet combining", MMSE FDE and packet combining are jointly performed at the chip-level. ii) In the second scheme, namely "symbol-level turbo packet combining", chip-level MMSE FDE and despreading are separately carried out for each transmission, then packet combining is performed at the level of the soft demapper. The computational complexity and memory requirements of both techniques are quite insensitive to the ARQ delay, i.e., maximum number of ARQ rounds. The throughput is evaluated for some representative antenna configurations and load factors to show the gains offered by the proposed techniques.Comment: Submitted to IEEE Transactions on Vehicular Technology (Apr 2009