FPGA implementation of an OFDM-based WLAN receiver

This paper deals with the design and implementation on FPGA of a receiver for OFDM-based WLAN. The circuit is particularized for IEEE 802.11a/g standards. The system includes frame detection, time and frequency synchronization, demodulation, equalization and phase tracking. The algorithms to be implemented for each task are selected taking into account performance, hardware cost and latency. Also, a fixed point analysis is made for each algorithm. Our objective is to maintain the PER loss below 0.5 dB for a PER = 10 -2, 64-QAM and error correction. The whole system is composed of two main blocks (correlator and CORDIC) that are reused in different time intervals to perform all the necessary operations, so the required hardware resources are minimized. To verify it, the receiver is physically implemented and tested. © 2011 Elsevier B.V. All rights reserved.This work was supported by the Spanish Ministerio de Educacion y Ciencia under grant TEC2008-06787.Canet Subiela, MJ.; Valls Coquillat, J.; Almenar Terré, V.; Marín-Roig Ramón, J. (2012). FPGA implementation of an OFDM-based WLAN receiver. Microprocessors and Microsystems. 36(3):232-244. https://doi.org/10.1016/j.micpro.2011.11.004S23224436

Design and implementation of synchronization and AGC for OFDM-based WLAN receivers

An efficient implementation of several tasks at the receiver becomes crucial in OFDM-based high-speed WLAN systems, such as automatic gain control, time and frequency synchronization and offset tracking. This paper deals with fixed point constraints and accuracy requirements for implementation of those algorithms. Also, a complete set of thresholds for the practical implementation of time and frequency synchronization sub-blocks is obtained. Moreover, a technique to mitigate the remaining frequency offset after coarse acquisition is proposed, yielding a good trade-off between performance and complexity. Finally, we propose the implementation of a simple and effective automatic gain control procedure.This work has been partially funded by Spanish government with project TIC 2002-03498 (ORISE), Telefonica I+D by the contract nº 25756, and the Chamber of Madrid Community and European Social Fund by a grant to the first author

Low Complexity Time Synchronization Algorithm for OFDM Systems with Repetitive Preambles

In this paper, a new time synchronization algorithm for OFDM systems with repetitive preamble is proposed. This algorithm makes use of coarse and fine time estimation; the fine time estimation is performed using a cross-correlation similar to previous proposals in the literature, whereas the coarse time estimation is made using a new metric and an iterative search of the last sample of the repetitive preamble. A complete analysis of the new metric is included, as well as a wide performance comparison, for multipath channel and carrier frequency offset, with the main time synchronization algorithms found in the literature. Finally, the complexity of the VLSI implementation of this proposal is discussed. © 2011 Springer Science+Business Media, LLC.This work was supported by the Spanish Ministerio de Educacion y Ciencia under grants TEC2006-14204-C02-01 and TEC2008-06787.Canet Subiela, MJ.; Almenar Terre, V.; Flores Asenjo, SJ.; Valls Coquillat, J. (2012). Low Complexity Time Synchronization Algorithm for OFDM Systems with Repetitive Preambles. Journal of Signal Processing Systems. 68(3):287-301. doi:10.1007/s11265-011-0618-6S287301683IEEE 802.11a standard (1999). Wireless LAN medium access control (MAC) and physical layer (PHY) specifications: high-speed physical layer in the 5 GHz band.IEEE 802.11 g standard (2003). Wireless LAN specifications: Further higher data rate extension in the 2.4 GHz band.IEEE 802.16-2004 (2004). Standard for local and metropolitan area networks, part 16: Air interface for fixed broadband wireless access systems.Lee, D., & Cheun, K. (2002). Coarse symbol synchronization algorithms for OFDM systems in multipath channels. IEEE Communications Letters, 6(10), 446–448.Park, B., Cheon, H., Ko, E., Kang, C., & Hong, D. (2004). A blind OFDM synchronization algorithm based on cyclic correlation. IEEE Signal Processing Letters, 11(2), 83–85.Beek, J. J., Sandell, M., & Börjesson, P. O. (1997). ML estimation of time and frequency offset in OFDM system. IEEE Transactions on Signal Processing, 45(7), 1800–1805.Ma, S., Pan, X., Yang, G., & Ng, T. (2009). Blind symbol synchronization based on cyclic prefix for OFDM systems. IEEE Transactions on Vehicular Technology, 58(4), 1746–1751.Schmidl, T., & Cox, D. (1997). Robust frequency and timing synchronization for OFDM. IEEE Transactions on Communications, 45(12), 1613–1621.Coulson, A. J. (2001). Maximum likelihood synchronization for OFDM using a pilot symbol: Algorithms. IEEE Journal on Selected Areas in Communications, 19(12), 2495–2503.Tufvesson, F., Edfors, O., & Faulker, M. (1999). Time and frequency synchronization for OFDM using PN-sequence preambles. Proceedings of the Vehicular Technology Conference (VTC), 4, 2203–2207.Shi, K., & Serpedin, E. (2004). Coarse frame and carrier synchronization of OFDM systems: a new metric and comparison. IEEE Transactions on Wireless Communications, 3(4), 1271–1284.Minn, H., Zeng, M., & Bhargava, V. K. (2000). On timing offset estimation for OFDM Systems. IEEE Communications Letters, 4, 242–244.Minn, H., Bhargava, V. K., & Letaief, K. B. (2003). A robust timing and frequency synchronization for OFDM systems. IEEE Transactions on Wireless Communications, 2(4), 822–839.Minn, H., Bhargava, V. K., & Letaief, K. B. (2006). A combined timing and frequency synchronization and channel estimation for OFDM. IEEE Transactions on Communications, 54(3), 416–422.Park, B., Cheon, H., Ko, E., Kang, C., & Hong, D. (2003). A novel timing estimation method for OFDM systems. IEEE Communications Letters, 7(5), 239–241.Chang, S., & Kelley, B. (2003). Time synchronization for OFDM-based WLAN systems. Electronics Letters, 39(13), 1024–1026.Wu, Y., Yip, K., Ng, T., & Serpedin, E. (2005). Maximum-likelihood symbol synchronization for IEEE 802.11a WLANs in unknown frequency-selective fading channels. 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A new symbol timing synchronization for OFDM based WLANs under multipath fading channels. 15th IEEE International Symposium on Personal, Indoor and Mobile Radio Communications. doi: 10.1109/PIMRC.2004.1373890 .Kim, T., & Park, S.-C. (2007). A new symbol timing and frequency synchronization design for OFDM-based WLAN systems. 9th Conference on Advanced Communication Technology. doi: 10.1109/ICACT.2007.358691 .Baek, J. H., Kim, S. D., & Sunwoo, M. H. (2008). SPOCS: Application specific signal processor for OFDM communication systems. Journal of Signal Processing Systems, 53(3), 383–397.Van Kempen, G., & van Vliet, L. (2000). Mean and variance of ratio estimators used in fluorescence ratio imaging. Cytometry, 39(4), 300–305.J. Melbo, J., & Schramm, P. (1998). Channel models for HIPERLAN/2 in different indoor scenarios. 3ERI085B, HIPERLAN/2 ETSI/BRAN contribution.Abramowitz, M., & Stegun, I. A. (1972). Handbook of mathematical functions. Dover.López-Martínez, F. J., del Castillo-Sánchez, E., Entrambasaguas, J. T., & Martos-Naya, E. (2010). Iterative-gradient based complex divider FPGA core with dynamic configurability of accuracy and throughput. Journal of Signal Processing Systems. doi: 10.1007/s11265-010-0464-y .Angarita, F., Canet, M. J., Sansaloni, T., Perez-Pascual, A., & Valls, J. (2008). Efficient mapping of CORDIC Algorithm for OFDM-based WLAN. Journal of Signal Processing Systems, 52(2), 181–191

A digital polar transmitter for multi-band OFDM Ultra-WideBand

Linear power amplifiers used to implement the Ultra-Wideband standard must be backed off from optimum power efficiency to meet the standard specifications and the power efficiency suffers. The problem of low efficiency can be mitigated by polar modulation. Digital polar architectures have been employed on numerous wireless standards like GSM, EDGE, and WLAN, where the fractional bandwidths achieved are only about 1%, and the power levels achieved are often in the vicinity of 20 dBm. Can the architecture be employed on wireless standards with low-power and high fractional bandwidth requirements and yet achieve good power efficiency? To answer these question, this thesis studies the application of a digital polar transmitter architecture with parallel amplifier stages for UWB. The concept of the digital transmitter is motivated and inspired by three factors. First, unrelenting advances in the CMOS technology in deep-submicron process and the prevalence of low-cost Digital Signal processing have resulted in the realization of higher level of integration using digitally intensive approaches. Furthermore, the architecture is an evolution of polar modulation, which is known for high power efficiency in other wireless applications. Finally, the architecture is operated as a digital-to-analog converter which circumvents the use of converters in conventional transmitters. Modeling and simulation of the system architecture is performed on the Agilent Advanced Design System Ptolemy simulation platform. First, by studying the envelope signal, we found that envelope clipping results in a reduction in the peak-to-average power ratio which in turn improves the error vector magnitude performance (figure of merit for the study). In addition, we have demonstrated that a resolution of three bits suffices for the digital polar transmitter when envelope clipping is performed. Next, this thesis covers a theoretical derivation for the estimate of the error vector magnitude based on the resolution, quantization and phase noise errors. An analysis on the process variations - which result in gain and delay mismatches - for a digital transmitter architecture with four bits ensues. The above studies allow RF designers to estimate the number of bits required and the amount of distortion that can be tolerated in the system. Next, a study on the circuit implementation was conducted. A DPA that comprises 7 parallel RF amplifiers driven by a constant RF phase-modulated signal and 7 cascode transistors (individually connected in series with the bottom amplifiers) digitally controlled by a 3-bit digitized envelope signal to reconstruct the UWB signal at the output. Through the use of NFET models from the IBM 130-nm technology, our simulation reveals that our DPA is able to achieve an EVM of - 22 dB. The DPA simulations have been performed at 3.432 GHz centre frequency with a channel bandwidth of 528 MHz, which translates to a fractional bandwidth of 15.4%. Drain efficiencies of 13.2/19.5/21.0% have been obtained while delivering -1.9/2.5/5.5 dBm of output power and consuming 5/9/17 mW of power. In addition, we performed a yield analysis on the digital polar amplifier, based on unit-weighted and binary-weighted architecture, when gain variations are introduced in all the individual stages. The dynamic element matching method is also introduced for the unit-weighted digital polar transmitter. Monte Carlo simulations reveal that when the gain of the amplifiers are allowed to vary at a mean of 1 with a standard deviation of 0.2, the binary-weighted architecture obtained a yield of 79%, while the yields of the unit-weighted architectures are in the neighbourhood of 95%. Moreover, the dynamic element matching technique demonstrates an improvement in the yield by approximately 3%. Finally, a hardware implementation for this architecture based on software-defined arbitrary waveform generators is studied. In this section, we demonstrate that the error vector magnitude results obtained with a four-stage binary-weighted digital polar transmitter under ideal combining conditions fulfill the European Computer Manufacturers Association requirements. The proposed experimental setup, believed to be the first ever attempted, confirm the feasibility of a digital polar transmitter architecture for Ultra-Wideband. In addition, we propose a number of power combining techniques suitable for the hardware implementation. Spatial power combining, in particular, shows a high potential for the digital polar transmitter architecture. The above studies demonstrate the feasibility of the digital polar architecture with good power efficiency for a wideband wireless standard with low-power and high fractional bandwidth requirements

Studio e realizzazione di un'architettura VLSI di un processore per l'implementazione dell'algoritmo FFT

Poiché lo standard di connessione 5G è utilizzato da un numero sempre crescente di dispositivi e si sta evolvendo per soddisfare nuove esigenze e requisiti, è diventato fondamentale studiare e progettare nuovi trasmettitori e ricevitori più veloci ed efficienti. Un ruolo fondamentale nella connessione 5G è svolto dal multiplexing a divisione di frequenza ortogonale (OFDM), una metodologia di modulazione. Poiché la demodulazione è basata sulla trasformata di Fourier, lo scopo di questa tesi è realizzare un processore in grado di implementare algoritmi FFT e DFT su sequenze di lunghezza variabile che rispetti i criteri dello standard 5G. Per fare ciò, è stata prima condotta un'analisi del rapporto dell'Unione internazionale delle telecomunicazioni ITU-R M.2410-0 per definire i requisiti minimi per il processore. Successivamente, uno studio dello stato dell'arte per dispositivi simili ha portato allo sviluppo di un'architettura VLSI adatta all'applicazione. Una versione RTL dell'architettura è stata implementata in VHDL e testata.Since the 5G connection standard is utilized by a rising number of devices and is evolving to meet new needs and requirements, it has become crucial to study and design new, faster, and more efficient transmitters and receivers. A fundamental role in the 5G connection is played by Orthogonal frequency-division multiplexing (OFDM), an encoding methodology. Since the demodulation is based on the Fourier Transform, the purpose of this thesis is to realize a processor capable of implementing FFT and DFT algorithms on variable length sequences that complies with the 5G standard criteria. In order to do so, first an analysis of the International Telecommunication Union report ITU-R M.2410-0 has been conducted to define the minimum requirements for the processor. Then, a study of the state of the art for similar devices led to the development of a VLSI architecture suitable for the application. An RTL version of the architecture has been implemented in VHDL and tested

FPGA Based Design & Implementation of Orthogonal Frequency Division Multiplexing Transciever Module using VHDL”,

ABSTRACT Orthogonal Frequency Division Multiplexing (OFDM) is a multi-carrier transmission technique, which divides the available spectrum into many carriers, each one being modulated by a low rate data stream. OFDM is similar to FDMA in that the multiple user access is achieved by subdividing the available bandwidth into multiple channels that are then allocated to users. However, OFDM uses the spectrum much more efficiently by spacing the channels much closer together. This is achieved by making all the carriers orthogonal to one another, preventing interference between the closely spaced carriers. The OFDM modem developed in this work consists of development of serial to parallel converter, 4-QAM modulator, IFFT logic which is built using 64 point radix-4 butterfly structure, FFT logic, 4-QAM de-modulator, and parallel-to-serial converter. The OFDM modem core is simulated by considering 31 sub-carriers. The whole design has been implemented using Xilinx Spartan-3AN XC3S700AN FPGA. The FFT/IFFT module that has been implemented makes use of CORDIC algorithms as an alternate for multipliers. This makes better usage of FPGA resources and the performance is more due to the usage of CORDIC algorithms instead of multipliers

FPGA Based Design & Implementation of Orthogonal Frequency Division Multiplexing Transciever Module using VHDL”,

ABSTRACT Orthogonal Frequency Division Multiplexing (OFDM) is a multi-carrier transmission technique, which divides the available spectrum into many carriers, each one being modulated by a low rate data stream. OFDM is similar to FDMA in that the multiple user access is achieved by subdividing the available bandwidth into multiple channels that are then allocated to users. However, OFDM uses the spectrum much more efficiently by spacing the channels much closer together. This is achieved by making all the carriers orthogonal to one another, preventing interference between the closely spaced carriers. The OFDM modem developed in this work consists of development of serial to parallel converter, 4-QAM modulator, IFFT logic which is built using 64 point radix-4 butterfly structure, FFT logic, 4-QAM de-modulator, and parallel-to-serial converter. The OFDM modem core is simulated by considering 31 sub-carriers. The whole design has been implemented using Xilinx Spartan-3AN XC3S700AN FPGA. The FFT/IFFT module that has been implemented makes use of CORDIC algorithms as an alternate for multipliers. This makes better usage of FPGA resources and the performance is more due to the usage of CORDIC algorithms instead of multipliers

Implementing carrier recovery for LTE 20 MHz on transport triggered architecture

Synchronization is a critical function in digital communications. Its failure may cause catastrophic effects on the transmission system performance. It is very important that the receiver is synchronised with the transmitter because it is not possible to correct frequencies/phases without any control mechanisms. Synchronization is different in Third Generation Partnership Project (3GPP) Long Term Evolution (LTE) for uplink and downlink because of the choice of multiple access scheme. Multiple access scheme for LTE downlink is Orthogonal Frequency Division Multiple Access (OFDMA) and Single Carrier-Frequency Division Multiple Access (SC-FDMA) for the uplink. OFDMA is susceptible to Carrier Frequency Offset (CFO). In case of a typical LTE system with a carrier frequency of 2.1 GHz, a frequency drift of 10ppm (10×10-6) of the local oscillator can cause an offset of 21 kHz. LTE system employs a fixed subcarrier spacing of 15 kHz. This offset caused by the local oscillator corresponds to 1.40 subcarrier spac-ings. The receiver extracts the information from the received signal to synchronise and compensate for any carrier frequency/phase offset. Increasing demand for data driven applications has put stress on communication systems to provide high data rates and increased bandwidth. This demand has ever been increasing and requires new standards to evolve and efficient hardware. It has been difficult to develop hardware at the pace new communication standards are developing. It also increases the cost of deployment of a technology for a brief period of time without covering the huge capital invested in the network. In order to meet the pace of evolving standards and covering the huge net-work costs, industry needs Software-Defined Radio (SDR). SDR is a radio communica-tion technology that is based on software defined wireless communication protocols instead of hardwired implementations. System components that are usually implemented in hardware are implemented by means of software on a computer or embedded system. LTE carrier recovery algorithm for LTE downlink with 20 MHz system bandwidth has been implemented in this thesis. The architecture chosen for implementation is Transport Triggered Architecture (TTA) with the goal to achieve real time constraints along with a certain flexibility and power consumption needed for an SDR platform. The target programming language is C with TTA specific extensions instead of hand optimized assembly with the aim to reduce the whole design time and still achieve the required optimizations and throughput. This design cycle time is also one of the im-portant aspects for product development in the industry

Singular value decomposition based pipeline architecture for MIMO communication systems

This thesis presents a design, implementation and performance benchmark of custom hardware for computing Singular Value Decomposition (SVD) of the radio communication channel characteristic matrix. Software Defined Radio (SDR) is a concept in which the radio transceiver is implemented by software programs running on a processor. SVD of the channel characteristic matrix is used in pre-coding, equalization and beamforming for Multiple Input Multiple Output (MIMO) and Orthogonal Frequency Division Modulation (OFDM) communication systems (e.g., IEEE 802.11n). Since SVD is computationally intensive, it may require custom hardware to reduce the computing time. The pipeline processor developed in this thesis is suitable for computing the SVD of a sequence of 2 × 2 matrices. A stream of 2×2 matrices is sent to the custom hardware, which returns the corresponding streams of singular values and unitary matrices. The architecture is based on the two sided Jacobi method utilizing Coordinate Rotation Digital Computer (CORDIC) algorithms. A 2×2 SVD prototype was implemented on Field-Programmable Gate Array (FPGA) for SDR applications. The 2×2 SVD prototype design can output the singular values and the corresponding unitary matrices in pipeline while operating at a data rate of 324 MHz on a Virtex 6 (xc6vlx240t-lff1156) FPGA. The prototype design consists of fifty-five CORDIC cores which takes 32 percent of available logic on the FPGA. It achieves the optimal pipeline rate equaled to the maximum hardware clock rate. The depth of the pipeline (latency) is 173 clock-cycles for 16-bit data hardware. The proposed architecture provides performance gains over standard software libraries, such as the ZGESVD function of Linear Algebra PACKage (LAPACK) library, which is based on Golub-Kahan-Reinsch SVD algorithm, when running on standard processors. The ZGESVD function of LAPACK implemented in Intel’s Math Kernel Library (MKL) will achieve a projected data rate of 40 MHz on a 2.50 GHz Intel Quad (Q9300) CPU. The pipeline SVD hardware ban width equals the clock frequency and the data rate can reach 324 MHz on the ML605 board (Virtex 6 xc6vlx240t). The proposed architecture also has the potential to be easily extended to solve 4×4 SVD problems used in pre-coding and equalization schemes. The proposed algorithm and design have better performance for small matrices, even though the general timing complexity is n2 when compared to nlog(n) complexity of Brent-Luk-Van Loan (BLV) systolic array using non-pipeline 2×2 processors. The performance gain of the proposed design is at the cost of increased circuit area.M.S., Computer Engineering -- Drexel University, 201

Design and implementation of a downlink MC-CDMA receiver

Cette thèse présente une étude d'un système complet de transmission en liaison descendante utilisant la technologie multi-porteuse avec l'accès multiple par division de code (Multi-Carrier Code Division Multiple Access, MC-CDMA). L'étude inclut la synchronisation et l'estimation du canal pour un système MC-CDMA en liaison descendante ainsi que l'implémentation sur puce FPGA d'un récepteur MC-CDMA en liaison descendante en bande de base. Le MC-CDMA est une combinaison de la technique de multiplexage par fréquence orthogonale (Orthogonal Frequency Division Multiplexing, OFDM) et de l'accès multiple par répartition de code (CDMA), et ce dans le but d'intégrer les deux technologies. Le système MC-CDMA est conçu pour fonctionner à l'intérieur de la contrainte d'une bande de fréquence de 5 MHz pour les modèles de canaux intérieur/extérieur pédestre et véhiculaire tel que décrit par le "Third Genaration Partnership Project" (3GPP). La composante OFDM du système MC-CDMA a été simulée en utilisant le logiciel MATLAB dans le but d'obtenir des paramètres de base. Des codes orthogonaux à facteur d'étalement variable (OVSF) de longueur 8 ont été choisis comme codes d'étalement pour notre système MC-CDMA. Ceci permet de supporter des taux de transmission maximum jusquà 20.6 Mbps et 22.875 Mbps (données non codées, pleine charge de 8 utilisateurs) pour les canaux intérieur/extérieur pédestre et véhiculaire, respectivement. Une étude analytique des expressions de taux d'erreur binaire pour le MC-CDMA dans un canal multivoies de Rayleigh a été réalisée dans le but d'évaluer rapidement et de façon précise les performances. Des techniques d'estimation de canal basées sur les décisions antérieures ont été étudiées afin d'améliorer encore plus les performances de taux d'erreur binaire du système MC-CDMA en liaison descendante. L'estimateur de canal basé sur les décisions antérieures et utilisant le critère de l'erreur quadratique minimale linéaire avec une matrice' de corrélation du canal de taille 64 x 64 a été choisi comme étant un bon compromis entre la performance et la complexité pour une implementation sur puce FPGA. Une nouvelle séquence d'apprentissage a été conçue pour le récepteur dans la configuration intérieur/extérieur pédestre dans le but d'estimer de façon grossière le temps de synchronisation et le décalage fréquentiel fractionnaire de la porteuse dans le domaine du temps. Les estimations fines du temps de synchronisation et du décalage fréquentiel de la porteuse ont été effectués dans le domaine des fréquences à l'aide de sous-porteuses pilotes. Un récepteur en liaison descendante MC-CDMA complet pour le canal intérieur /extérieur pédestre avec les synchronisations en temps et en fréquence en boucle fermée a été simulé avant de procéder à l'implémentation matérielle. Le récepteur en liaison descendante en bande de base pour le canal intérieur/extérieur pédestre a été implémenté sur un système de développement fabriqué par la compagnie Nallatech et utilisant le circuit XtremeDSP de Xilinx. Un transmetteur compatible avec le système de réception a également été réalisé. Des tests fonctionnels du récepteur ont été effectués dans un environnement sans fil statique de laboratoire. Un environnement de test plus dynamique, incluant la mobilité du transmetteur, du récepteur ou des éléments dispersifs, aurait été souhaitable, mais n'a pu être réalisé étant donné les difficultés logistiques inhérentes. Les taux d'erreur binaire mesurés avec différents nombres d'usagers actifs et différentes modulations sont proches des simulations sur ordinateurs pour un canal avec bruit blanc gaussien additif