17 research outputs found

    Landing AI on Networks: An equipment vendor viewpoint on Autonomous Driving Networks

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    The tremendous achievements of Artificial Intelligence (AI) in computer vision, natural language processing, games and robotics, has extended the reach of the AI hype to other fields: in telecommunication networks, the long term vision is to let AI fully manage, and autonomously drive, all aspects of network operation. In this industry vision paper, we discuss challenges and opportunities of Autonomous Driving Network (ADN) driven by AI technologies. To understand how AI can be successfully landed in current and future networks, we start by outlining challenges that are specific to the networking domain, putting them in perspective with advances that AI has achieved in other fields. We then present a system view, clarifying how AI can be fitted in the network architecture. We finally discuss current achievements as well as future promises of AI in networks, mentioning a roadmap to avoid bumps in the road that leads to true large-scale deployment of AI technologies in networks

    Measurement of Triple-Differential Z+Jet Cross Sections with the CMS Detector at 13 TeV and Modelling of Large-Scale Distributed Computing Systems

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    The achievable precision in the calculations of predictions for observables measured at the LHC experiments depends on the amount of invested computing power and the precision of input parameters that go into the calculation. Currently, no theory exists that can derive the input parameter values for perturbative calculations from first principles. Instead, they have to be derived from measurements in dedicated analyses that measure observables sensitive to the input parameters with high precision. Such an analysis that measures the production cross section of oppositely charged muon pairs with an invariant mass close to the mass of the Z\mathrm{Z} boson in association with jets in a phase space divided into bins of the transverse momentum of the dimuon system pTZp_T^\text{Z}, and two observables yy^* and yby_b created from the rapidities of the dimuon system and the jet with the highest momentum is presented. To achieve the highest statistical precision in this triple-differential measurement the full data recorded by the CMS experiment at a center-of-mass energy of s=13TeV\sqrt{s}=13\,\mathrm{TeV} in the years 2016 to 2018 is combined. The measured cross sections are compared to theoretical predictions approximating full NNLO accuracy in perturbative QCD. Deviations from these predictions are observed rendering further studies at full NNLO accuracy necessary. To obtain the measured results large amounts of data are processed and analysed on distributed computing infrastructures. Theoretical calculations pose similar computing demands. Consequently, substantial amounts of storage and processing resources are required by the LHC collaborations. These requirements are met in large parts by the resources of the WLCG, a complex federation of globally distributed computer centres. With the upgrade of the LHC and the experiments, in the HL-LHC era, the computing demands are expected to increase substantially. Therefore, the prevailing computing models need to be updated to cope with the unprecedented demands. For the design of future adaptions of the HEP workflow executions on infrastructures a simulation model is developed, and an implementation tested on infrastructure design candidates inspired by a proposal of the German HEP computing community. The presented study of these infrastructure candidates showcases the applicability of the simulation tool in the strategical development of a future computing infrastructure for HEP in the HL-LHC context

    US LHCNet: Transatlantic Networking for the LHC and the U.S. HEP Community

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    Performance-aware energy optimizations in networks for HPC

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    Energy efficiency is an important challenge in the field of High Performance Computing (HPC). High energy requirements not only limit the potential to realize next-generation machines but are also an increasing part of the total cost of ownership of an HPC system. While at large HPC systems are becoming increasingly energy proportional in an effort to reduce energy costs, interconnect links stand out for their inefficiency. Commodity interconnect links remain ¿always-on¿, consuming full power even when no data is being transmitted. Although various techniques have been proposed towards energy- proportional interconnects, they are often too conservative or are not focused toward HPC. Aggressive techniques for interconnect energy savings are often not applied to HPC, in particular, because they may incur excessive performance overheads. Any energy-saving technique will only be adopted in HPC if there is no significant impact on performance, which is still the primary design objective. This thesis explores interconnect energy proportionality from a performance perspective. In this thesis, first a characterization of HPC applications is presented, making a case for the enormous potential for interconnect energy proportionality with HPC applications. Next, an HPC interconnect with on/off based links, modeled after the IEEE Energy Efficient Ethernet protocol, is evaluated. This evaluation while presenting a relationship between performance impact and energy over HPC applications also emphasizes the need for performance focused designs in energy efficient interconnects. Next, an adaptive mechanism, PerfBound, is presented that saves link energy subject to a bound on application performance overheads. Finally this evaluation structure is applied into an intermediate link power state, in addition to the traditional on and off states. Results of this study, over 15 production HPC applications show that, compared to current day always-on HPC interconnects, link energy can be reduced by unto 70%, while application performance overhead is bounded to only 1%.La eficiencia energética es un gran reto en el área de la Supercomputación (HPC), las grandes necesidades de energía no solo limitan el potencial de las computadoras de nueva generación, sino que también aumentan el coste de funcionamiento de estos sistemas. Mientras que los sistemas HPC tienden a ser cada vez más energéticamente proporcionales en un empeño por reducir costes, los enlaces de interconexión siguen siendo muy ineficientes. Los enlaces de interconexión comunes funcionan en modo "always-on", es decir, consumiendo energía incluso cuando no transmiten. Aunque se han propuesto algunas técnicas que ayuden a la proporcionalidad energética de los enlaces de interconexión, éstas han sido muy agresivas o poco enfocadas hacia su uso con sistemas HPC. Las técnicas de ahorro energético para los enlaces más agresivas no suelen ser utilizadas en HPC, particularmente porque degradan excesivamente el rendimiento. Cualquier técnica de ahorro energético solo será adoptada en sistemas HPC si no hay un impacto excesivo en el rendimiento, el cual es el principal objetivo de estos sistemas. En esta tesis, primeramente se presenta una nueva caracterización de aplicaciones HPC, remarcando el enorme potencial de la proporcionalidad en los enlaces de interconexión proporcionales para aplicaciones HPC. Seguidamente, se evaluará siguiendo el protocolo "IEEE Energy Efficient Ethernet" un link de interconexión on/off. Esta evaluación presentará una relación de impacto energético y rendimiento en aplicaciones HPC, enfatizando en la necesidad de usar un enlace de interconexión enfocados a la eficiencia. Se continuará con la presentación de un mecanismo adaptivo, PerfBound, que ahorra energía respetando unos límites máximos de impacto en el rendimiento. Finalmente, esta estructura es aplicada a un nuevo estado intermedio de funcionamiento adicional a los estados tradicionales on/off. Los resultados de este estudio, muestran que en más de 15 aplicaciones HPC la energía en los enlaces puede ser reducida en un 70% en comparación con enlaces "always-on", mientras que el impacto en el rendimiento es de tan solo un 1%.Postprint (published version

    Multi-Core Parallel Routing

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    The recent increase in the amount of data (i.e., big data) led to higher data volumes to be transferred and processed over the network. Also, over the last years, the deployment of multi-core routers has grown rapidly. However, such big data transfers are not leveraging the powerful multi-core routers to the extent possible, particularly in the key function of routing. Our main goal is to find a way so we can use these cores more effectively and efficiently in routing the big data transfers. In this dissertation, we propose a novel approach to parallelize data transfers by leveraging the multi-core CPUs in the routers. Legacy routing protocols, e.g. OSPF for intra-domain routing, send data from source to destination on a shortest single path. We describe an end-to-end method to distribute data optimally on flows by using multiple paths. We generate new virtual topology substrates from the underlying router topology and perform shortest path routing on each substrate. With this framework, even though calculating shortest paths could be done with well-known techniques such as OSPF's Dijkstra implementation, finding optimal substrates so as to maximize the aggregate throughput over multiple end-to-end paths is still an NP-hard problem. We focus our efforts on solving the problem and design heuristics for substrate generation from a given router topology. Our heuristics' interim goal is to generate substrates in such a way that the shortest path between a source-destination pair on each substrate minimally overlaps with each other. Once these substrates are determined, we assign each substrate to a core in routers and employ a multi-path transport protocol, like MPTCP, to perform end-to-end parallel transfers

    HEP Science Network Requirements--Final Report

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    Development of electronics for the VELO upgrade detector

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    Esta tesis cubre el diseño electrónico del detector de vértices (VELO) del experimento LHCb del CERN. El VELO está situado rodeando el punto de colisión de los dos haces de protones del LHC del CERN. Su diseño está lleno de restricciones que requieren diseños novedosos: minimizar la materia cerca del punto de colisión, diseño de componentes que soporten radiación, transmisión de datos a alta tasa y el procesado de los mismos, sincronización del sistema, etc. El trabajo presentado en esta tesis se centra en: por un lado, la validación del hardware y sus diferentes prototipos, por otro lado, el diseño del firmware de las FPGAs encargadas del control, sincronización y adquisición de datos del VELO
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