Compiling Geometric Algebra Computations into Reconfigurable Hardware Accelerators

Geometric Algebra (GA), a generalization of quaternions and complex numbers, is a very powerful framework for intuitively expressing and manipulating the complex geometric relationships common to engineering problems. However, actual processing of GA expressions is very compute intensive, and acceleration is generally required for practical use. GPUs and FPGAs offer such acceleration, while requiring only low-power per operation. In this paper, we present key components of a proof-of-concept compile flow combining symbolic and hardware optimization techniques to automatically generate hardware accelerators from the abstract GA descriptions that are suitable for high-performance embedded computing

Articulating Space: Geometric Algebra for Parametric Design -- Symmetry, Kinematics, and Curvature

To advance the use of geometric algebra in practice, we develop computational methods for parameterizing spatial structures with the conformal model. Three discrete parameterizations – symmetric, kinematic, and curvilinear – are employed to generate space groups, linkage mechanisms, and rationalized surfaces. In the process we illustrate techniques that directly benefit from the underlying mathematics, and demonstrate how they might be applied to various scenarios. Each technique engages the versor – as opposed to matrix – representation of transformations, which allows for structure-preserving operations on geometric primitives. This covariant methodology facilitates constructive design through geometric reasoning: incidence and movement are expressed in terms of spatial variables such as lines, circles and spheres. In addition to providing a toolset for generating forms and transformations in computer graphics, the resulting expressions could be used in the design and fabrication of machine parts, tensegrity systems, robot manipulators, deployable structures, and freeform architectures. Building upon existing algorithms, these methods participate in the advancement of geometric thinking, developing an intuitive spatial articulation that can be creatively applied across disciplines, ranging from time-based media to mechanical and structural engineering, or reformulated in higher dimensions

Advances in Robot Kinematics : Proceedings of the 15th international conference on Advances in Robot Kinematics

International audienceThe motion of mechanisms, kinematics, is one of the most fundamental aspect of robot design, analysis and control but is also relevant to other scientific domains such as biome- chanics, molecular biology, . . . . The series of books on Advances in Robot Kinematics (ARK) report the latest achievement in this field. ARK has a long history as the first book was published in 1991 and since then new issues have been published every 2 years. Each book is the follow-up of a single-track symposium in which the participants exchange their results and opinions in a meeting that bring together the best of world’s researchers and scientists together with young students. Since 1992 the ARK symposia have come under the patronage of the International Federation for the Promotion of Machine Science-IFToMM.This book is the 13th in the series and is the result of peer-review process intended to select the newest and most original achievements in this field. For the first time the articles of this symposium will be published in a green open-access archive to favor free dissemination of the results. However the book will also be o↵ered as a on-demand printed book.The papers proposed in this book show that robot kinematics is an exciting domain with an immense number of research challenges that go well beyond the field of robotics.The last symposium related with this book was organized by the French National Re- search Institute in Computer Science and Control Theory (INRIA) in Grasse, France

Rapid Prototyping and Exploration Environment for Generating C-to-Hardware-Compilers

There is today an ever-increasing demand for more computational power coupled with a desire to minimize energy requirements. Hardware accelerators currently appear to be the best solution to this problem. While general purpose computation with GPUs seem to be very successful in this area, they perform adequately only in those cases where the data access patterns and utilized algorithms fit the underlying architecture. ASICs on the other hand can yield even better results in terms of performance and energy consumption, but are very inflexible, as they are manufactured with an application specific circuitry. Field Programmable Gate Arrays (FPGAs) represent a combination of approaches: With their application specific hardware they provide high computational power while requiring, for many applications, less energy than a CPU or a GPU. On the other hand they are far more flexible than an ASIC due to their reconfigurability. The only remaining problem is the programming of the FPGAs, as they are far more difficult to program compared to regular software. To allow common software developers, who have at best very limited knowledge in hardware design, to make use of these devices, tools were developed that take a regular high level language and generate hardware from it. Among such tools, C-to-HDL compilers are a particularly wide-spread approach. These compilers attempt to translate common C code into a hardware description language from which a datapath is generated. Most of these compilers have many restrictions for the input and differ in their underlying generated micro architecture, their scheduling method, their applied optimizations, their execution model and even their target hardware. Thus, a comparison of a certain aspect alone, like their implemented scheduling method or their generated micro architecture, is almost impossible, as they differ in so many other aspects. This work provides a survey of the existing C-to-HDL compilers and presents a new approach to evaluating and exploring different micro architectures for dynamic scheduling used by such compilers. From a mathematically formulated rule set the Triad compiler generates a backend for the Scale compiler framework, which then implements a hardware generation backend with described dynamic scheduling. While more than a factor of four slower than hardware from highly optimized compilers, this environment allows easy comparison and exploration of different rule sets and the micro architecture for the dynamically scheduled datapaths generated from them. For demonstration purposes a rule set modeling the COCOMA token flow model from the COMRADE 2.0 compiler was implemented. Multiple variants of it were explored: Savings of up to 11% of the required hardware resources were possible

Applied Mathematics to Mechanisms and Machines

This book brings together all 16 articles published in the Special Issue "Applied Mathematics to Mechanisms and Machines" of the MDPI Mathematics journal, in the section “Engineering Mathematics”. The subject matter covered by these works is varied, but they all have mechanisms as the object of study and mathematics as the basis of the methodology used. In fact, the synthesis, design and optimization of mechanisms, robotics, automotives, maintenance 4.0, machine vibrations, control, biomechanics and medical devices are among the topics covered in this book. This volume may be of interest to all who work in the field of mechanism and machine science and we hope that it will contribute to the development of both mechanical engineering and applied mathematics