Quantum Reed-Solomon Codes

After a brief introduction to both quantum computation and quantum error correction, we show how to construct quantum error-correcting codes based on classical BCH codes. With these codes, decoding can exploit additional information about the position of errors. This error model - the quantum erasure channel - is discussed. Finally, parameters of quantum BCH codes are provided.Comment: Summary only (2 pages), for the full version see: Proceedings Applied Algebra, Algebraic Algorithms and Error-Correcting Codes (AAECC-13), Lecture Notes in Computer Science 1719, Springer, 199

Hardware/Software Co-design Applied to Reed-Solomon Decoding for the DMB Standard

This paper addresses the implementation of Reed- Solomon decoding for battery-powered wireless devices. The scope of this paper is constrained by the Digital Media Broadcasting (DMB). The most critical element of the Reed-Solomon algorithm is implemented on two different reconfigurable hardware architectures: an FPGA and a coarse-grained architecture: the Montium, The remaining parts are executed on an ARM processor. The results of this research show that a co-design of the ARM together with an FPGA or a Montium leads to a substantial decrease in energy consumption. The energy consumption of syndrome calculation of the Reed- Solomon decoding algorithm is estimated for an FPGA and a Montium by means of simulations. The Montium proves to be more efficient

Complexity Analysis of Reed-Solomon Decoding over GF(2^m) Without Using Syndromes

For the majority of the applications of Reed-Solomon (RS) codes, hard decision decoding is based on syndromes. Recently, there has been renewed interest in decoding RS codes without using syndromes. In this paper, we investigate the complexity of syndromeless decoding for RS codes, and compare it to that of syndrome-based decoding. Aiming to provide guidelines to practical applications, our complexity analysis differs in several aspects from existing asymptotic complexity analysis, which is typically based on multiplicative fast Fourier transform (FFT) techniques and is usually in big O notation. First, we focus on RS codes over characteristic-2 fields, over which some multiplicative FFT techniques are not applicable. Secondly, due to moderate block lengths of RS codes in practice, our analysis is complete since all terms in the complexities are accounted for. Finally, in addition to fast implementation using additive FFT techniques, we also consider direct implementation, which is still relevant for RS codes with moderate lengths. Comparing the complexities of both syndromeless and syndrome-based decoding algorithms based on direct and fast implementations, we show that syndromeless decoding algorithms have higher complexities than syndrome-based ones for high rate RS codes regardless of the implementation. Both errors-only and errors-and-erasures decoding are considered in this paper. We also derive tighter bounds on the complexities of fast polynomial multiplications based on Cantor's approach and the fast extended Euclidean algorithm.Comment: 11 pages, submitted to EURASIP Journal on Wireless Communications and Networkin

Symbol level decoding of Reed-Solomon codes with improved reliability information over fading channels

A thesis submitted to the Faculty of Engineering and the Built Environment, University of the Witwatersrand, Johannesburg, in fulfilment of the requirements for the degree of Doctor of Philosophy in the School of Electrical and Information Engineering, 2016Reliable and e cient data transmission have been the subject of current research, most especially in realistic channels such as the Rayleigh fading channels. The focus of every new technique is to improve the transmission reliability and to increase the transmission capacity of the communication links for more information to be transmitted. Modulation schemes such as M-ary Quadrature Amplitude Modulation (M-QAM) and Orthogonal Frequency Division Multiplexing (OFDM) were developed to increase the transmission capacity of communication links without additional bandwidth expansion, and to reduce the design complexity of communication systems. On the contrary, due to the varying nature of communication channels, the message transmission reliability is subjected to a couple of factors. These factors include the channel estimation techniques and Forward Error Correction schemes (FEC) used in improving the message reliability. Innumerable channel estimation techniques have been proposed independently, and in combination with di erent FEC schemes in order to improve the message reliability. The emphasis have been to improve the channel estimation performance, bandwidth and power consumption, and the implementation time complexity of the estimation techniques. Of particular interest, FEC schemes such as Reed-Solomon (RS) codes, Turbo codes, Low Density Parity Check (LDPC) codes, Hamming codes, and Permutation codes, are proposed to improve the message transmission reliability of communication links. Turbo and LDPC codes have been used extensively to combat the varying nature of communication channels, most especially in joint iterative channel estimation and decoding receiver structures. In this thesis, attention is focused on using RS codes to improve the message reliability of a communication link because RS codes have good capability of correcting random and burst errors, and are useful in di erent wireless applications. This study concentrates on symbol level soft decision decoding of RS codes. In this regards, a novel symbol level iterative soft decision decoder for RS codes based on parity-check equations is developed. This Parity-check matrix Transformation Algorithm (PTA) is based on the soft reliability information derived from the channel output in order to perform syndrome checks in an iterative process. Performance analysis verify that this developed PTA outperforms the conventional RS hard decision decoding algorithms and the symbol level Koetter and Vardy (KV ) RS soft decision decoding algorithm. In addition, this thesis develops an improved Distance Metric (DM) method of deriving reliability information over Rayleigh fading channels for combined demodulation with symbol level RS soft decision decoding algorithms. The newly proposed DM method incorporates the channel state information in deriving the soft reliability information over Rayleigh fading channels. Analysis verify that this developed metric enhances the performance of symbol level RS soft decision decoders in comparison with the conventional method. Although, in this thesis, the performance of the developed DM method of deriving soft reliability information over Rayleigh fading channels is only veri ed for symbol level RS soft decision decoders, it is applicable to any symbol level soft decision decoding FEC scheme. Besides, the performance of the all FEC decoding schemes plummet as a result of the Rayleigh fading channels. This engender the development of joint iterative channel estimation and decoding receiver structures in order to improve the message reliability, most especially with Turbo and LDPC codes as the FEC schemes. As such, this thesis develops the rst joint iterative channel estimation and Reed- Solomon decoding receiver structure. Essentially, the joint iterative channel estimation and RS decoding receiver is developed based on the existing symbol level soft decision KV algorithm. Consequently, the joint iterative channel estimation and RS decoding receiver is extended to the developed RS parity-check matrix transformation algorithm. The PTA provides design ease and exibility, and lesser computational time complexity in an iterative receiver structure in comparison with the KV algorithm. Generally, the ndings of this thesis are relevant in improving the message transmission reliability of a communication link with RS codes. For instance, it is pertinent to numerous data transmission technologies such as Digital Audio Broadcasting (DAB), Digital Video Broadcasting (DVB), Digital Subscriber Line (DSL), WiMAX, and long distance satellite communications. Equally, the developed, less computationally intensive, and performance e cient symbol level decoding algorithm for RS codes can be use in consumer technologies like compact disc and digital versatile disc.GS201

Architectures for soft-decision decoding of non-binary codes

En esta tesis se estudia el dise¿no de decodificadores no-binarios para la correcci'on de errores en sistemas de comunicaci'on modernos de alta velocidad. El objetivo es proponer soluciones de baja complejidad para los algoritmos de decodificaci'on basados en los c'odigos de comprobaci'on de paridad de baja densidad no-binarios (NB-LDPC) y en los c'odigos Reed-Solomon, con la finalidad de implementar arquitecturas hardware eficientes. En la primera parte de la tesis se analizan los cuellos de botella existentes en los algoritmos y en las arquitecturas de decodificadores NB-LDPC y se proponen soluciones de baja complejidad y de alta velocidad basadas en el volteo de s'¿mbolos. En primer lugar, se estudian las soluciones basadas en actualizaci'on por inundaci 'on con el objetivo de obtener la mayor velocidad posible sin tener en cuenta la ganancia de codificaci'on. Se proponen dos decodificadores diferentes basados en clipping y t'ecnicas de bloqueo, sin embargo, la frecuencia m'axima est'a limitada debido a un exceso de cableado. Por este motivo, se exploran algunos m'etodos para reducir los problemas de rutado en c'odigos NB-LDPC. Como soluci'on se propone una arquitectura basada en difusi'on parcial para algoritmos de volteo de s'¿mbolos que mitiga la congesti'on por rutado. Como las soluciones de actualizaci 'on por inundaci'on de mayor velocidad son sub-'optimas desde el punto de vista de capacidad de correci'on, decidimos dise¿nar soluciones para la actualizaci'on serie, con el objetivo de alcanzar una mayor velocidad manteniendo la ganancia de codificaci'on de los algoritmos originales de volteo de s'¿mbolo. Se presentan dos algoritmos y arquitecturas de actualizaci'on serie, reduciendo el 'area y aumentando de la velocidad m'axima alcanzable. Por 'ultimo, se generalizan los algoritmos de volteo de s'¿mbolo y se muestra como algunos casos particulares puede lograr una ganancia de codificaci'on cercana a los algoritmos Min-sum y Min-max con una menor complejidad. Tambi'en se propone una arquitectura eficiente, que muestra que el 'area se reduce a la mitad en comparaci'on con una soluci'on de mapeo directo. En la segunda parte de la tesis, se comparan algoritmos de decodificaci'on Reed- Solomon basados en decisi'on blanda, concluyendo que el algoritmo de baja complejidad Chase (LCC) es la soluci'on m'as eficiente si la alta velocidad es el objetivo principal. Sin embargo, los esquemas LCC se basan en la interpolaci'on, que introduce algunas limitaciones hardware debido a su complejidad. Con el fin de reducir la complejidad sin modificar la capacidad de correcci'on, se propone un esquema de decisi'on blanda para LCC basado en algoritmos de decisi'on dura. Por 'ultimo se dise¿na una arquitectura eficiente para este nuevo esquemaGarcía Herrero, FM. (2013). Architectures for soft-decision decoding of non-binary codes [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/33753TESISPremiad

New Decoding of Reed-Solomon Codes Based on FFT and Modular Approach

Decoding algorithms for Reed--Solomon (RS) codes are of great interest for both practical and theoretical reasons. In this paper, an efficient algorithm, called the modular approach (MA), is devised for solving the Welch--Berlekamp (WB) key equation. By taking the MA as the key equation solver, we propose a new decoding algorithm for systematic RS codes. For $(n,k)$ RS codes, where $n$ is the code length and $k$ is the code dimension, the proposed decoding algorithm has both the best asymptotic computational complexity $O(n\log(n-k) + (n-k)\log^2(n-k))$ and the smallest constant factor achieved to date. By comparing the number of field operations required, we show that when decoding practical RS codes, the new algorithm is significantly superior to the existing methods in terms of computational complexity. When decoding the $(4096, 3584)$ RS code defined over $\mathbb{F}_{2^{12}}$, the new algorithm is 10 times faster than a conventional syndrome-based method. Furthermore, the new algorithm has a regular architecture and is thus suitable for hardware implementation

Constructions of Rank Modulation Codes

Rank modulation is a way of encoding information to correct errors in flash memory devices as well as impulse noise in transmission lines. Modeling rank modulation involves construction of packings of the space of permutations equipped with the Kendall tau distance. We present several general constructions of codes in permutations that cover a broad range of code parameters. In particular, we show a number of ways in which conventional error-correcting codes can be modified to correct errors in the Kendall space. Codes that we construct afford simple encoding and decoding algorithms of essentially the same complexity as required to correct errors in the Hamming metric. For instance, from binary BCH codes we obtain codes correcting $t$ Kendall errors in $n$ memory cells that support the order of $n!/(\log_2n!)^t$ messages, for any constant $t= 1,2,...$ We also construct families of codes that correct a number of errors that grows with $n$ at varying rates, from $\Theta(n)$ to $\Theta(n^{2})$. One of our constructions gives rise to a family of rank modulation codes for which the trade-off between the number of messages and the number of correctable Kendall errors approaches the optimal scaling rate. Finally, we list a number of possibilities for constructing codes of finite length, and give examples of rank modulation codes with specific parameters.Comment: Submitted to IEEE Transactions on Information Theor

A VLSI synthesis of a Reed-Solomon processor for digital communication systems

The Reed-Solomon codes have been widely used in digital communication systems such as computer networks, satellites, VCRs, mobile communications and high- definition television (HDTV), in order to protect digital data against erasures, random and burst errors during transmission. Since the encoding and decoding algorithms for such codes are computationally intensive, special purpose hardware implementations are often required to meet the real time requirements. -- One motivation for this thesis is to investigate and introduce reconfigurable Galois field arithmetic structures which exploit the symmetric properties of available architectures. Another is to design and implement an RS encoder/decoder ASIC which can support a wide family of RS codes. -- An m-programmable Galois field multiplier which uses the standard basis representation of the elements is first introduced. It is then demonstrated that the exponentiator can be used to implement a fast inverter which outperforms the available inverters in GF(2m). Using these basic structures, an ASIC design and synthesis of a reconfigurable Reed-Solomon encoder/decoder processor which implements a large family of RS codes is proposed. The design is parameterized in terms of the block length n, Galois field symbol size m, and error correction capability t for the various RS codes. The design has been captured using the VHDL hardware description language and mapped onto CMOS standard cells available in the 0.8-µm BiCMOS design kits for Cadence and Synopsys tools. The experimental chip contains 218,206 logic gates and supports values of the Galois field symbol size m = 3,4,5,6,7,8 and error correction capability t = 1,2,3, ..., 16. Thus, the block length n is variable from 7 to 255. Error correction t and Galois field symbol size m are pin-selectable. -- Since low design complexity and high throughput are desired in the VLSI chip, the algebraic decoding technique has been investigated instead of the time or transform domain. The encoder uses a self-reciprocal generator polynomial which structures the codewords in a systematic form. At the beginning of the decoding process, received words are initially stored in the first-in-first-out (FIFO) buffer as they enter the syndrome module. The Berlekemp-Massey algorithm is used to determine both the error locator and error evaluator polynomials. The Chien Search and Forney's algorithms operate sequentially to solve for the error locations and error values respectively. The error values are exclusive or-ed with the buffered messages in order to correct the errors, as the processed data leave the chip