189 research outputs found

    Design of LMS algorithm for noise canceller based on FPGA

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    This paper presents the design of an adapting filtering method to remove the noise in the biomedical signal records. The major concern about analyze the presence of various artifacts in ECG records and modular artifacts in EEG records caused due to various noise factors. Here, we have proposed a design based on LMS (Least Mean Square) algorithm to remove the artifacts from biomedical signal using Verilog HDL based on been mapped on  commercially available FPGAs (Field Programmable Gate Arrays). In this design the LMS algorithm used as a noise canceller and the reference signal was adaptively filtered and subtracted from primary signal to obtain the estimated biomedical signal. The original biomedical signal can be reconstructed by passing the digital bit stream through a low pass filter. This design is suitable for its low power biomedical instrument design and it reduces the whole system cost. Keywords: LMS algorithm, noise canceller, Verilog HDL, artifacts, biomedical signal, Low power application

    Robust Automatic Speech recognition System Implemented in a Hybrid Design DSP-FPGA

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    The aim of this work is to reduce the burden task on the DSP processor by transferring a parallel computation part on a configurable circuits FPGA, in automatic speech recognition module design, signal pre-processing, feature selection and optimization, models construction and finally classification phase are necessary. LMS filter algorithm that contains more parallelism and more MACs (multiply and Accumulate) operations is implemented on FPGA Virtex 5 by Xilings, MFCCs features extraction and DTW ( dynamic time wrapping) method is used as a classifier. Major contribution of this work are hybrid solution DSP and FPGA in real time speech recognition system design, the optimization of number of MAC-core within the FPGA this result is obtained by sharing MAC resources between two operation phases: computation of output filter and updating LMS filter coefficients. The paper also provides a hardware solution of the filter with detailed description of asynchronous interface of FPGA circuit and TMS320C6713-EMIF component. The results of simulation shows an improvement in time computation and by optimizing the implementation on the FPGA a gain in space consumption is obtained

    Realization of Delayed Least Mean Square Adaptive Algorithm using Verilog HDL for EEG Signals

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    An efficient architecture for the implementation of delayed least mean square (DLMS) adaptive filter is presented in this paper. It is shown that the proposed architectures reduces the register complexity and also supports the faster convergence. Compared to transpose form, the direct form LMS adaptive filter has fast convergence but both has most similar critical path. Further it is shown that in most of the practical cases, very small adaptation delay is sufficient enough to implement a direct-form LMS adaptive filter where in normal cases a very high sampling rate is required and also it shows that no pipelining approach is necessary. From the above discussed estimations three different architectures of LMS adaptive filter has been designed. They are, first design comprise of zero delays i.e., with no adaptation delays, second design comprises of only single delay i.e., with only one adaptation delay, and lastly the third design comprises of two adaptation delays. Among all the three designs zero adaptation delay structure gives efficient performance comparatively. Design with zero adaptation delay involves the minimum energy per sample (EPS) and also minimum area compared to other two designs. The aim of this thesis is to design an efficient filter structures to create a system-on-chip (SoC) solution by using an optimized code for solving various adaptive filtering problems in the system. In this thesis our main focus is on interference cancellation in electroencephalogram (EEG) applications by using the proposed filter structures. Modern field programmable gate arrays (FPGAs) have the resources that are required to design an effective adaptive filtering structures. The designs are evaluated in terms of design time, area and delays

    A novel fixed-point leaky sign regressor algorithm based adaptive noise canceller for PLI cancellation in ECG signals

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    In this paper, a novel fixed-point Leaky Sign Regressor Algorithm (LSRA) based adaptive noise canceller has been employed for the cancellation of 60 Hz Power Line Interference (PLI) from the ElectroCardioGram (ECG) signal. A sufficient condition for the convergence in the mean of the LSRA algorithm is also derived. The fixed-point LSRA-based adaptive noise canceller employed in this work is fully quantized using an in-house quantize function. The most effective number of quantization bits required for the various parameters are found to be 6-bits and are determined through rigorous simulations. The filtered ECG signal free from 60 Hz PLI is successfully recovered using a novel 6-bit fixed-point LSRA-based adaptive noise canceller

    Efficient FPGA implementation of Recursive Least Square adaptive filter using non-restoring division algorithm

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    In this paper, Recursive Least Square (RLS) and Affine Projection (AP) adaptive filters are designed using Xilinx System Generator and implemented on the Spartan6 xc6slx16-2csg324 FPGA platform. FPGA platform utilizes the non-restoring division algorithm and the COordinate Rotation DIgital Computer (CORDIC) division algorithm to perform the division task of the RLS and AP adaptive filters. The Non-restoring division algorithm demonstrates efficient performance in terms of convergence speed and signal-to-noise ratio. In contrast, the CORDIC division algorithm requires 31 cycles for division initialization, whereas the non-restoring algorithm initializes division in just one cycle. To validate the effectiveness of the proposed filters, a set of ten ECG records from the BIT-MIT database is used to test their ability to remove Power Line Interference (PLI) noise from the ECG signal. The proposed adaptive filters are compared with various adaptive algorithms in terms of Signal-to-Noise Ratio (SNR), convergence speed, residual noise, steady-state Mean Square Error (MSE), and complexity

    Measuring the Phase Variation of a DOCSIS 3.1 Full Duplex Channel

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    Including a Full Duplex option into DOCSIS introduces several problems. One of the more troublesome issues is the presence of a strong self interference signal that leaks from the transmit side to the receive side of a cable node. This self interference is caused by echoes in the channel that translate the forward travelling transmit signals into a reverse travelling signal, as well as, by leakage from the hybrid coupler used to couple the upstream and downstream signals. To suppress this self interference an echo canceller is implemented to remove the unwanted interference from the received signal. Unfortunately with the high rates of data transmission used in modern day CATV networks the echo canceller needs tremendous precision. A major concern in the implementation of Full Duplex into DOCSIS is if the channels used are even very slightly time varying. The echos in such channels change with time and can be difficult for the echo canceller to track. Changes in the response of the channel cause the echo profile of the network to shift and the echo canceler to re-adapt to the new channel response. The issue with this changing response is that it is possible for the channel to change faster than the echo canceller can adapt, resulting in the interference becoming unacceptably high. Since the channel is a physical network of coaxial cables often exposed to the environment, its propagation properties can be affected by wind swaying pole mounted cables, or by rapid heating from the sun, or sudden shifts in the load of the network. With information on how the physical properties of the cable changes, the engineers designing the echo canceller can know how fast the canceller must adapt to changes and also have a better measure of how reliable its echo cancellation will be. In this thesis the stability of the echo profile of the channel is measured. It is shown that the property of the channel with the greatest potential to rapidly change and cause noise after echo cancellation is the phase response of the channel. Due to this, the approach of this thesis is to measure the fluctuations in the phase of the channel response of a CATV network constructed in the lab. To measure the fluctuations in the phase response of the channel, a PLL (Phase Locked Loop) based circuit is designed and built on an FPGA (Field Programmable Gate Array) and connected to a model of a simple CATV network. The PLL circuit used to measure the phase fluctuations of the channel is designed to be able to measure changes occurring faster than 0.1 Hz and with a power higher than 107V210^{-7} \: V^2. The circuit is able to capture data from the channel over a period of 90 seconds. Using this phase variation measurement circuit a series of experiments were performed on a model CATV DOCSIS network. It was found that many physical disturbances to the network had the effect of rapidly shifting the phase response of the network. Heating the cables in the network was found to shift the phase response upwards of 20000μ20000\:\muradians. Flexing the cables in the network was found to have a peak phase variation of 8000μ8000\: \muradians with similar effects found from walking over cables. Overall, it was clear that physical effects on the network had the propensity to rapidly shift the network response. Any echo canceller that is designed in the future will have to consider these effects when reporting the cancellation that it is able to achieve

    Hardware Implementation of Neural Self-Interference Cancellation

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    In-band full-duplex systems can transmit and receive information simultaneously on the same frequency band. However, due to the strong self-interference caused by the transmitter to its own receiver, the use of non-linear digital self-interference cancellation is essential. In this work, we describe a hardware architecture for a neural network-based non-linear self-interference (SI) canceller and we compare it with our own hardware implementation of a conventional polynomial based SI canceller. In particular, we present implementation results for a shallow and a deep neural network SI canceller as well as for a polynomial SI canceller. Our results show that the deep neural network canceller achieves a hardware efficiency of up to 312.8312.8 Msamples/s/mm2^2 and an energy efficiency of up to 0.90.9 nJ/sample, which is 2.1×2.1\times and 2×2\times better than the polynomial SI canceller, respectively. These results show that NN-based methods applied to communications are not only useful from a performance perspective, but can also be a very effective means to reduce the implementation complexity.Comment: Accepted for publication in IEEE Journal on Emerging and Selected Topics in Circuits and System

    Novel implementation technique for a wavelet-based broadband signal detection system

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    This thesis reports on the design, simulation and implementation of a novel Implementation for a Wavelet-based Broadband Signal Detection System. There is a strong interest in methods of increasing the resolution of sonar systems for the detection of targets at sea. A novel implementation of a wideband active sonar signal detection system is proposed in this project. In the system the Continuous Wavelet Transform is used for target motion estimation and an Adaptive-Network-based Fuzzy inference System (ANFIS) is adopted to minimize the noise effect on target detection. A local optimum search algorithm is introduced in this project to reduce the computation load of the Continuous Wavelet Transform and make it suitable for practical applications. The proposed system is realized on a Xilinx University Program Virtex-II Pro Development System which contains a Virtex II pro XC2VP30 FPGA chip with 2 powerPC 405 cores. Testing for single target detection and multiple target detection shows the proposed system is able to accurately locate targets under reverberation-limited underwater environment with a Signal-Noise-Ratio of up to -30db, with location error less than 10 meters and velocity estimation error less than 1 knot. In the proposed system the combination of CWT and local optimum search algorithm significantly saves the computation time for CWT and make it more practical to real applications. Also the implementation of ANFIS on the FPGA board indicates in the future a real-time ANFIS operation with VLSI implementation would be possible

    Performance of an Echo Canceller and Channel Estimator for On-Channel Repeaters in DVB-T/H Networks

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    This paper investigates the design and performance of an FIR echo canceller for on-channel repeaters in DVB-T/H network within the framework of the PLUTO project. The possible approaches for echo cancellation are briefly reviewed and the main guidelines for the design of such systems are presented. The main system parameters are discussed. The performance of an FIR echo canceller based on an open loop feedforward approach for channel estimation is tested for different radio channel conditions and for different number of taps of the FIR filter. It is shown that a minimum number of taps is recommended to achieve a certain mean rejection ratio or isolation depending on the type of channel. The expected degradation in performance due to the use of fixed point rather than floating point arithmetic in hardware implementation is presented for different number of bits. Channel estimation based on training sequences is investigated. The performance of Maximum Length Sequences and Constant Amplitude Zero Autocorrelation (CAZAC) Sequences is compared for different channels. Recommendations are given for training sequence type, length and level for DVB-T/H on-channel repeater deployment

    VLSI Design and Implementation for Adaptive Filter using LMS Algorithm

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    Adaptive filters, as part of digital signal systems, have been widely used, as well as in applications such as adaptive noise cancellation, adaptive beam forming, channel equalization, and system identification. However, its implementation takes a great deal and becomes a very important field in digital system world. When FPGA (Field Programmable Logic Array) grows in area and provides a lot of facilities to the designers, it becomes an important competitor in the signal processing market. In general FIR structure has been used more successfully than IIR structure in adaptive filters. However, when the adaptive FIR filter was made this required appropriate algorithm to update the filter’s coefficients. The algorithm used to update the filter coefficient is the Least Mean Square (LMS) algorithm which is known for its simplification, low computational complexity, and better performance in different running environments. When compared to other algorithms used for implementing adaptive filters the LMS algorithm is seen to perform very well in terms of the number of iterations required for convergence. This phenomenon can be achieved by a sufficient choice of bit length to represent the filter’s coefficients. This paper presents a lowcost and high performance programmable digital finite impulse response (FIR) filter. It follows the adaptive algorithm used for the development of the system. The architecture employs the computation sharing algorithm to reduce the computation complexity
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