Design of a GF(64)-LDPC Decoder Based on the EMS Algorithm

International audienceThis paper presents the architecture, performance and implementation results of a serial GF(64)-LDPC decoder based on a reduced-complexity version of the Extended Min-Sum algorithm. The main contributions of this work correspond to the variable node processing, the codeword decision and the elementary check node processing. Post-synthesis area results show that the decoder area is less than 20% of a Virtex 4 FPGA for a decoding throughput of 2.95 Mbps. The implemented decoder presents performance at less than 0.7 dB from the Belief Propagation algorithm for different code lengths and rates. Moreover, the proposed architecture can be easily adapted to decode very high Galois Field orders, such as GF(4096) or higher, by slightly modifying a marginal part of the design

One minimum only trellis decoder for non-binary low-density parity-check codes

© 2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.A one minimum only decoder for Trellis-EMS (OMO T-EMS) and for Trellis-Min-max (OMO T-MM) is proposed in this paper. In this novel approach, we avoid computing the second minimum in messages of the check node processor, and propose efficient estimators to infer the second minimum value. By doing so, we greatly reduce the complexity and at the same time improve latency and throughput of the derived architectures compared to the existing implementations of EMS and Min-max decoders. This solution has been applied to various NB-LDPC codes constructed over different Galois fields and with different degree distributions showing in all cases negligible performance loss compared to the ideal EMS and Min-max algorithms. In addition, two complete decoders for OMO T-EMS and OMO T-MM were implemented for the (837,726) NB-LDPC code over GF(32) for comparison proposals. A 90 nm CMOS process was applied, achieving a throughput of 711 Mbps and 818 Mbps respectively at a clock frequency of 250 MHz, with an area of 19.02 ${rm mm}^{2}$ and 16.10 ${rm mm}^{2}$ after place and route. To the best knowledge of the authors, the proposed decoders have higher throughput and area-time efficiency than any other solution for high-rate NB-LDPC codes with high Galois field order.This work was supported in part by the Spanish Ministerio de Ciencia e Innovacion under Grant TEC2011-27916 and in part by the Universitat Politecnica de Valencia under Grant PAID-06-2012-SP20120625. The work of F. Garcia-Herrero was supported by the Spanish Ministerio de Educacion under Grant AP2010-5178. David Declercq has been funded by the Institut Universitaire de France for this project. This paper was recommended by Associate Editor Z. Zhang.Lacruz, JO.; García Herrero, FM.; Valls Coquillat, J.; Declercq, D. (2015). One minimum only trellis decoder for non-binary low-density parity-check codes. IEEE Transactions on Circuits and Systems I: Regular Papers. 62(1):177-184. https://doi.org/10.1109/TCSI.2014.2354753S17718462

Parallel Nonbinary LDPC Decoding on GPU

Nonbinary Low-Density Parity-Check (LDPC) codes are a class of error-correcting codes constructed over the Galois field GF(q) for q > 2. As extensions of binary LDPC codes, nonbinary LDPC codes can provide better error-correcting performance when the code length is short or moderate, but at a cost of higher decoding complexity. This paper proposes a massively parallel implementation of a nonbinary LDPC decoding accelerator based on a graphics processing unit (GPU) to achieve both great flexibility and scalability. The implementation maps the Min-Max decoding algorithm to GPU’s massively parallel architecture. We highlight the methodology to partition the decoding task to a heterogeneous platform consisting of the CPU and GPU. The experimental results show that our GPUbased implementation can achieve high throughput while still providing great flexibility and scalability.National Science Foundation (NSF

Reduction of Complexity for Nonbinary LDPC Decoders With Compressed Messages

© 2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.In this brief, a method for compressing the messages between check nodes and variable nodes is proposed. This method is named compressed nonbinary message passing (CNBMP). CNBMP reduces the number of messages exchanged between one check node and the connected variable nodes from d(c) x q to 5 x q, and its application has a high impact on the performance of the decoder: the storage and routing areas are reduced and the throughput is increased. Unlike other methods, CNBMP does not introduce any approximation or modification in the information and the processed operations are exactly the same as those of the original decoders; hence, no performance degradation is introduced. To demonstrate its advantages, an architecture applying this CNBMP to the Trellis Min-Max algorithm was derived showing that most of the storage resources were also reduced from dc x q to 5 x q. This architecture was implemented for a (837 726) nonbinary low-density parity-check code using a 90-nm CMOS technology reaching a throughput of 981 Mb/s with an area of 10.67 mm(2), which is 3.9 more efficient than the best solution found in the literature.This work was supported by the Spanish Ministerio de Ciencia e Innovacion under Grant TEC2011-27916. The work of F. Garcia-Herrero was supported by the Spanish Ministerio de Educacion through Formacion de Profesorado Universitario (FPU) under Grant AP2010-5178.Lacruz Jucht, JO.; García Herrero, FM.; Valls Coquillat, J. (2015). Reduction of Complexity for Nonbinary LDPC Decoders With Compressed Messages. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 23(11):2676-2679. https://doi.org/10.1109/TVLSI.2014.2377194S26762679231

Reduced-complexity Non-Binary LDPC decoder for high-order Galois fields based on Trellis Min-Max algorithm

© 2016 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.Non-binary LDPC codes outperform its binary counterparts in different scenarios. However, they require a considerable increase in complexity, especially in the check-node processor, for high-order Galois fields higher than GF(16). To overcome this drawback, we propose an approximation for the Trellis Min-Max algorithm which allows us to reduce the number of exchanged messages between check node and variable node compared to previous proposals from literature. On the other hand, we reduce the complexity in the check-node processor, keeping the parallel computation of messages. We implemented a layered scheduled decoder, based on this algorithm, in a 90nm CMOS technology for the (837,723) NB-LDPC code over GF(32) and the (1536,1344) over GF(64), achieving an area saving of 16% and 36% for the check-node and 10% and 12% for the whole decoder, respectively. The throughput is 1.07 Gbps and 1.26 Gbps, which outperforms the state-of-the-art of high-rate decoders with high GF order from literature.This work was supported in part by the Spanish Ministerio de Ciencia e Innovacion under Grant TEC2011-27916 and Grant TEC2012-38558-C02-02 and in part by Generalitat Valenciana under Grant GV/2014/011.Lacruz, JO.; García Herrero, FM.; Canet Subiela, MJ.; Valls Coquillat, J. (2016). Reduced-complexity Non-Binary LDPC decoder for high-order Galois fields based on Trellis Min-Max algorithm. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 1-11. https://doi.org/10.1109/TVLSI.2016.2514484S11