Effective network grid synthesis and optimization for high performance very large scale integration system design

制度:新 ; 文部省報告番号:甲2642号 ; 学位の種類:博士(工学) ; 授与年月日:2008/3/15 ; 早大学位記番号:新480

On the deployment of on-chip noise sensors

The relentless technology scaling has led to significantly reduced noise margin and complicated functionalities. As such, design time techniques per se are less likely to ensure power integrity, resulting in runtime voltage emergencies. To alleviate the issue, recently several works have shed light on the possibilities of dynamic noise management systems. Most of these works rely on on-chip noise sensors to accurately capture voltage emergencies. However, they all assume that the placement of the sensors is given. It remains an open problem in the literature how to optimally place a given number of noise sensors for best voltage emergency detection. The problem of noise sensor placement is defined at first along with a novel sensing quality metric (SQM) to be maximized. The threshold voltage for noise sensors to report emergencies serves as a critical tuning knob between the system failure rate and false alarms. The problem of minimizing the system alarm rate subject to a given system failure rate constraint is formulated. It is further shown that with the help of IDDQ measurements during testing which reveal process variation information, it is possible and efficient to compute a per-chip optimal threshold voltage threshold. In the third chapter, a novel framework to predict the resonance frequency using existing on-chip noise sensors, based on the theory of 1-bit compressed sensing is proposed. The proposed framework can help to achieve the resonance frequency of individual chips so as to effectively avoid resonance noise at runtime --Abstract, page iii

Clock Jitter in Communication Systems

For reliable digital communication between devices, the sources that contribute to data sampling errors must be properly modeled and understood. Clock jitter is one such error source occurring during data transfer between integrated circuits. Clock jitter is a noise source in a communication link similar to electrical noise, but is a time domain noise variable affecting many different parts of the sampling process. Presented in this dissertation, the clock jitter effect on sampling is modeled for communication systems with the degree of accuracy needed for modern high speed data communication. The models developed and presented here have been used to develop the clocking specifications and silicon budgets for industry standards such as PCI Express, USB3.0, GDDR5 Memory, and HBM Memory interfaces

A Charge-Recycling Scheme and Ultra Low Voltage Self-Startup Charge Pump for Highly Energy Efficient Mixed Signal Systems-On-A-Chip

The advent of battery operated sensor-based electronic systems has provided a pressing need to design energy-efficient, ultra-low power integrated circuits as a means to improve the battery lifetime. This dissertation describes a scheme to lower the power requirement of a digital circuit through the use of charge-recycling and dynamic supply-voltage scaling techniques. The novel charge-recycling scheme proposed in this research demonstrates the feasibility of operating digital circuits using the charge scavenged from the leakage and dynamic load currents inherent to digital design. The proposed scheme efficiently gathers the “ground-bound” charge into storage capacitor banks. This reclaimed charge is then subsequently recycled to power the source digital circuit. The charge-recycling methodology has been implemented on a 12-bit Gray-code counter operating at frequencies of less than 50 MHz. The circuit has been designed in a 90-nm process and measurement results reveal more than 41% reduction in the average energy consumption of the counter. The total energy savings including the power consumed for the generation of control signals aggregates to an average of 23%. The proposed methodology can be applied to an existing digital path without any design change to the circuit but with only small loss to the performance. Potential applications of this scheme are described, specifically in wide-temperature dynamic power reduction and as a source for energy harvesters. The second part of this dissertation deals with the design and development of a self-starting, ultra-low voltage, switched-capacitor (SC) DC-DC converter that is essential to an energy harvesting system. The proposed charge-pump based SC-converter operates from 125-mV input and thus enables battery-less operation in ultra-low voltage energy harvesters. The charge pump does not require any external components or expensive post-fabrication processing to enable low-voltage operation. This design has been implemented in a 130-nm CMOS process. While the proposed charge pump provides significant efficiency enhancement in energy harvesters, it can also be incorporated within charge recycling systems to facilitate adaptable charge-recycling levels. In total, this dissertation provides key components needed for highly energy-efficient mixed signal systems-on-a-chip

Analysis and modeling of power supply induced jitter for high speed driver and low dropout voltage regulator

”With the scaling of power supply voltage levels and improving trans-conductance of drivers, the sensitivity of drivers to power supply induced delays has increased. The power supply induced jitter (PSIJ) has become one of the major concerns for high-speed system. In this work, the PSIJ analysis and modeling method are proposed for high speed drivers and the system with on-die low dropout (LDO) voltage regulator. In addition, a jitter-aware target impedance concept is proposed for power distribution network (PDN) design to correlate the PSIJ with PDN parasitic. The proposed PSIJ analysis model is based on the driver power supply rejection ratio (PSRR) response, transition edge slope and the propagation delay. It is demonstrated that the proposed model can be generalized for different type of drivers. Following the proposed PSIJ model, a method for improving the PSIJ simulation accuracy in the input/output buffer information (IBIS) model is also proposed. A PSIJ analysis method is also proposed for system with on-die LDO. The approach relies on separate analysis of the LDO block PSRR response and the buffer block PSIJ sensitivity. This procedure allows designer to evaluate the system PSIJ with fewer and faster simulations. For the jitter-aware target impedance, a systematic procedure to develop the target impedance curves is formulated and developed for common CMOS buffer circuits. Given the transient IC switching current and the jitter specification, multiple target impedance curves can be defined for a specific circuit. The proposed design procedure can largely relieve over-constrain in the PDN designed based on the original target impedance definition”--Abstract, page iv

System and Circuit Design Techniques for Silicon-based Multi-band/Multi-standard Receivers

Today, the advances in Complementary MetalOxideSemiconductor (CMOS) technology have guided the progress in the wireless communications circuits and systems area. Various new communication standards have been developed to accommodate a variety of applications at different frequency bands, such as cellular communications at 900 and 1800 MHz, global positioning system (GPS) at 1.2 and 1.5 GHz, and Bluetooth andWiFi at 2.4 and 5.2 GHz, respectively. The modern wireless technology is now motivated by the global trend of developing multi-band/multistandard terminals for low-cost and multifunction transceivers. Exploring the unused 10-66 GHz frequency spectrum for high data rate communication is also another trend in the wireless industry. In this dissertation, the challenges and solutions for designing a multi-band/multistandard mobile device is addressed from system-level analysis to circuit implementation. A systematic system-level design methodology for block-level budgeting is proposed. The system-level design methodology focuses on minimizing the power consumption of the overall receiver. Then, a novel millimeter-wave dual-band receiver front-end architecture is developed to operate at 24 and 31 GHz. The receiver relies on a newly introduced concept of harmonic selection that helps to reduce the complexity of the dual-band receiver. Wideband circuit techniques for millimeterwave frequencies are also investigated and new bandwidth extension techniques are proposed for the dual-band 24/31 GHz receiver. These new techniques are applied for the low noise amplifier and millimeter-wave mixer resulting in the widest reported operating bandwidth in K-band, while consuming less power consumption. Additionally, various receiver building blocks, such as a low noise amplifier with reconfigurable input matching network for multi-band receivers, and a low drop-out regulator with high power supply rejection are analyzed and proposed. The low noise amplifier presents the first one with continuously reconfigurable input matching network, while achieving a noise figure comparable to the wideband techniques. The low drop-out regulator presented the first one with high power supply rejection in the mega-hertz frequency range. All the proposed building blocks and architecture in this dissertation are implemented using the existing silicon-based technologies, and resulted in several publications in IEEE Journals and Conferences

Modeling And Design Of Multi-port Dc/dc Converters

In this dissertation, a new satellite platform power architecture based on paralleled three-port DC/DC converters is proposed to reduce the total satellite power system mass. Moreover, a fourport DC/DC converter is proposed for renewable energy applications where several renewable sources are employed. Compared to the traditional two-port converter, three-port or four-port converters are classified as multi-port converters. Multi-port converters have less component count and less conversion stage than the traditional power processing solution which adopts several independent two-port converters. Due to their advantages multi-port converters recently have attracted much attention in academia, resulting in many topologies for various applications. But all proposed topologies have at least one of the following disadvantages: 1) no bidirectional port; 2) lack of proper isolation; 3) too many active and passive components; 4) no softswitching. In addition, most existing research focuses on the topology investigation, but lacks study on the multi-port converter’s control aspects, which are actually very challenging since it is a multi-input multi-output control system and has so many cross-coupled control loops. A three-port converter is proposed and used for space applications. The topology features bidirectional capability, low component count and soft-switching for all active switches, and has one output port to meet certain isolating requirements. For the system level control strategy, the multi-functional central controller has to achieve maximal power harvesting for the solar panel, the battery charge control for the battery, and output voltage regulation for the dc bus. In order to design these various controllers, a good dynamic model of the control object should be obtained first. Therefore, a modeling procedure based on a traditional state-space averaging method is v proposed to characterize the dynamic behavior of such a multi-port converter. The proposed modeling method is clear and easy to follow, and can be extended for other multi-port converters. In order to boost the power level of the multi-port converter system and allow redundancy, the three-port converters are paralleled together. The current sharing control for the multi-port converters has rarely been reported. A so called “dual loop” current sharing control structure is identified to be suitable for the paralleled multi-port converters, since its current loop and the voltage loop can be considered and designed independently, which simplifies the multi-port converter’s loop analysis. The design criteria for that dual loop structure are also studied to achieve good current sharing dynamics while guaranteeing the system stability. The renewable energy applications are continuously demanding the low cost solution, so that the renewable energy might have a more competitive dollar per kilowatt figure than the traditional fossil fuel power generation. For this reason, the multi-port converter is a good candidate for such applications due to the low component count and low cost. Especially when several renewable sources are combined to increase the power delivering certainty, the multi-port solution is more beneficial since it can replace more separate converters. A four-port converter is proposed to interface two different renewable sources, such as the wind turbine and the solar panel, one bidirectional battery device, and the galvanically isolated load. The four-port converter is based on the traditional half-bridge topology making it easy for the practicing power electronics engineer to follow the circuit design. Moreover, this topology can be extended into n input ports which allow more input renewable sources. vi Finally, the work is summarized and concluded, and references are listed