Fault-tolerant polyphase filters-based decimators for SRAM-based FPGA implementations

To reduce the oversampling rate of baseband signals, decimation is widely used in digital communication systems. Polyphase filters (PPFs) can be used to efficiently implement decimators. SRAM-based FPGAs provide large amounts of resources combined with flexibility and are a popular option for the implementation of communication receivers. However, they are sensitive to soft errors, which limit their application in harsh environments, such as space. An initial reliability study on SRAM-based FPGA implemented decimation shows that the soft errors on around 5% of the critical bits in the configuration memory of the decimator would degrade the decimated signal dramatically. Based on this result, this paper proposes an efficient fault tolerance scheme, in which the high correlation between adjacent PPFs outputs is utilized to tolerate the fault of a single-phase filter, and a duplicate and comparison structure is used to protect the fault tolerance logic. Hardware implementation and fault injection experiments show that the proposed scheme can drastically reduce the number of critical bits that cause severe output degradation with 1.5x resource usage and 0.75x maximum frequency relative to the unprotected decimator. Therefore, the proposed scheme can be an alternative to Triple Modular Redundancy that more than triples the use of resources.This work is supported by Natural Science Funds of China (Grant No. 62171313) and is partially supported by the ACHILLES project PID2019-104207RB-I00 funded by the Spanish Ministry of Science and Innovation and by the Madrid Community research project TAPIR-CM grant no. P2018/TCS-4496

On-board B-ISDN fast packet switching architectures. Phase 2: Development. Proof-of-concept architecture definition report

For the next-generation packet switched communications satellite system with onboard processing and spot-beam operation, a reliable onboard fast packet switch is essential to route packets from different uplink beams to different downlink beams. The rapid emergence of point-to-point services such as video distribution, and the large demand for video conference, distributed data processing, and network management makes the multicast function essential to a fast packet switch (FPS). The satellite's inherent broadcast features gives the satellite network an advantage over the terrestrial network in providing multicast services. This report evaluates alternate multicast FPS architectures for onboard baseband switching applications and selects a candidate for subsequent breadboard development. Architecture evaluation and selection will be based on the study performed in phase 1, 'Onboard B-ISDN Fast Packet Switching Architectures', and other switch architectures which have become commercially available as large scale integration (LSI) devices

A Survey on the Best Choice for Modulus of Residue Code

Nowadays, the development of technology and the growing need for dense and complex chips have led chip industries to increase their attention on the circuit testability. Also, using the electronic chips in certain industries, such as the space industry, makes the design of fault tolerant circuits a challenging issue. Coding is one of the most suitable methods for error detection and correction. The residue code, as one of the best choices for error detection aims, is wildly used in large arithmetic circuits such as multiplier and also finds a wide range of applications in processors and digital filters. The modulus value in this technique directly effect on the area overhead parameter. A large area overhead is one of the most important disadvantages especially for testing the small circuits. The purpose of this paper is to study and investigate the best choice for residue code check base that is used for simple and small circuits such as a simple ripple carry adder. The performances are evaluated by applying stuck-at-faults and transition-faults by simulators. The efficiency is defined based on fault coverage and normalized area overhead. The results show that the modulus 3 with 95% efficiency provided the best result. Residue code with this modulus for checking a ripple carry adder, in comparison with duplex circuit, 30% improves the efficiency

Digital Signal Processing Research Program

Contains table of contents for Section 2, an introduction, reports on twenty-two research projects and a list of publications.Sanders, a Lockheed-Martin Corporation Contract BZ4962U.S. Army Research Laboratory Contract DAAL01-96-2-0001U.S. Navy - Office of Naval Research Grant N00014-93-1-0686National Science Foundation Grant MIP 95-02885U.S. Navy - Office of Naval Research Grant N00014-96-1-0930National Defense Science and Engineering FellowshipU.S. Air Force - Office of Scientific Research Grant F49620-96-1-0072U.S. Navy - Office of Naval Research Grant N00014-95-1-0362National Science Foundation Graduate Research FellowshipAT&T Bell Laboratories Graduate Research FellowshipU.S. Army Research Laboratory Contract DAAL01-96-2-0002National Science Foundation Graduate FellowshipU.S. Army Research Laboratory/Advanced Sensors Federated Lab Program Contract DAAL01-96-2-000

Measurements, Models, Systems and Design

531 s.

Digital Signal Processing Research Program

Contains table of contents for Section 2, an introduction and reports on seventeen research projects.U.S. Navy - Office of Naval Research Grant N00014-91-J-1628Vertical Arrays for the Heard Island Experiment Award No. SC 48548Charles S. Draper Laboratories, Inc. Contract DL-H-418472Defense Advanced Research Projects Agency/U.S. Navy - Office of Naval Research Grant N00014-89-J-1489Rockwell Corporation Doctoral FellowshipMIT - Woods Hole Oceanographic Institution Joint ProgramDefense Advanced Research Projects Agency/U.S. Navy - Office of Naval Research Grant N00014-90-J-1109Lockheed Sanders, Inc./U.S. Navy - Office of Naval Research Contract N00014-91-C-0125U.S. Air Force - Office of Scientific Research Grant AFOSR-91-0034AT&T Laboratories Doctoral ProgramU.S. Navy - Office of Naval Research Grant N00014-91-J-1628General Electric Foundation Graduate Fellowship in Electrical EngineeringNational Science Foundation Grant MIP 87-14969National Science Foundation Graduate FellowshipCanada Natural Sciences and Engineering Research CouncilLockheed Sanders, Inc

Fault tolerance in space-based digital signal processing and switching systems: Protecting up-link processing resources, demultiplexer, demodulator, and decoder

Fault tolerance features in the first three major subsystems appearing in the next generation of communications satellites are described. These satellites will contain extensive but efficient high-speed processing and switching capabilities to support the low signal strengths associated with very small aperture terminals. The terminals' numerous data channels are combined through frequency division multiplexing (FDM) on the up-links and are protected individually by forward error-correcting (FEC) binary convolutional codes. The front-end processing resources, demultiplexer, demodulators, and FEC decoders extract all data channels which are then switched individually, multiplexed, and remodulated before retransmission to earth terminals through narrow beam spot antennas. Algorithm based fault tolerance (ABFT) techniques, which relate real number parity values with data flows and operations, are used to protect the data processing operations. The additional checking features utilize resources that can be substituted for normal processing elements when resource reconfiguration is required to replace a failed unit