Implementação e ambiente de validação em lógica programável de um decodificador LDPC

A concepção de um circuito integrado envolve uma sequência algorítmica de passos a serem cumpridos para transformar uma ideia em “silício”. De forma simplificada, um desses passos é a implementação de uma determinada lógica usando linguagens apropriadas para esta finalidade. Fundamentalmente é de suma importância efetivar testes e simulações nessa lógica, propiciando ao desenvolvedor menor risco financeiro, pois é uma oportunidade de encontrar defeitos e assim realizar novos e rápidos ciclos de projeto na lógica gerada. Com o intuito de realizar testes que demandariam excessivo tempo computacional de simulação na lógica em questão, é possível realizar a prototipação em lógica programável, em Field Programmable Gate Array (FPGA) e assim, fisicamente exercitar os circuitos digitais nela contida. Porém, para se realizar esta, é necessária a implementação não só do módulo de lógica em questão como também de uma infraestrutura adjacente para estimular o bloco e gerenciar os testes. Neste trabalho é proposta uma arquitetura para executar esses estímulos em um decodificador de correção de erros com estratégia LDPC. Para tal, é efetuada a implementação deste mesmo bloco, que fora anteriormente descrito pelo autor em HDL, juntamente com módulos de gerenciamento dos estímulos para exercitar e coletar os resultados.The conception of an integrated circuit involves an algorithmic sequence of steps to be followed to transform an idea into “silicon”. In a simplified way, one of these steps is the implementation of a certain logic, using languages appropriate for this task. Fundamentally, it is crucial to carry tests and simulations in this logic, providing the developer with less financial risk, as it is an opportunity to find defects and thus carry out new and fast design cycles in the generated logic. To carry out tests that would require excessive computational simulation time in the logic in question, it is possible to perform prototyping in programmable logic, in Field Programmable Gate Array (FPGA), and therefore, physically exercise the digital circuits contained therein. However, to perform, it is necessary to implement the logic module in question and adjacent infrastructure to stimulate the block and manage the tests. An architecture is proposed to execute these stimuli in an error correction decoder with the LDPC strategy in this work. To this end, the implementation of this same block is carried out, which was previously described by the author in HDL, together with modules for managing the stimuli to exercise and collect the results

Next-generation High-Capacity Communications with High Flexibility, Efficiency, and Reliability

The objective of this dissertation is to address the flexibility, efficiency and reliability in high-capacity heterogeneous communication systems. We will experimentally investigate the shaping techniques, and further extend them to more diverse and complicated scenarios, which result in more flexible systems. The scenarios include 1) entropy allocation scheme under uneven frequency response for multi-carrier system, 2) fiber-free space optics link using unipolar pairwise distribution, and 3) flexible rate passive optical network with a wide range of received optical powers. Next, we perform efficiency analysis in inter-data center and long-haul communications. We will characterize the impact of the laser linewidth, jitter tones, and the flicker noise on coherent systems with different baud rates and fiber lengths through theoretical analysis, simulation, and experimental validation. The trade-off analysis indicates the importance of setting up frequency noise power spectral density masks to qualify the transceiver laser design. Besides efficiency analysis, we will also work on efficient system architecture and algorithm design. We investigate the combined impact of various hardware impairments using proposed simplified DSP schemes in beyond 800G self-homodyne coherent system. The proposed scheme is very promising for next-generation intra-data center applications. On the other hand, to improve the data efficiency of the nonlinearity correction algorithm in broadband communication systems, we leverage the semi-supervised method and Lasso. Experimental results validate that Lasso can reduce the required pilot symbol number by exploiting the sparsity of the tap coefficients. Semi-supervised method can further enhance the system performance without introducing additional overhead. Last but not least, regarding reliability, we propose and experimentally demonstrate an ultra-reliable integrated millimeter wave and free space optics analog radio over fiber system with algorithm design. The multiple-spectra operation shows superior performance in reliability and sensitivity compared to the conventional systems, even in extreme weather conditions and strong burst interference.Ph.D

Modelling, Dimensioning and Optimization of 5G Communication Networks, Resources and Services

This reprint aims to collect state-of-the-art research contributions that address challenges in the emerging 5G networks design, dimensioning and optimization. Designing, dimensioning and optimization of communication networks resources and services have been an inseparable part of telecom network development. The latter must convey a large volume of traffic, providing service to traffic streams with highly differentiated requirements in terms of bit-rate and service time, required quality of service and quality of experience parameters. Such a communication infrastructure presents many important challenges, such as the study of necessary multi-layer cooperation, new protocols, performance evaluation of different network parts, low layer network design, network management and security issues, and new technologies in general, which will be discussed in this book