Resonant Circuit Topology for Radio Frequency Energy Harvesting

In this work the operation of a MOSFET based rectifier, composed of multiple stages of voltage doubler circuits used for radio frequency (RF) energy harvesting, is investigated. Analytical modeling of the input stage of the rectifier consisting of short-channel diode-connected transistors is carried out, and the equivalent input resistance obtained is used along with simulation results to improve impedance matching in the harvester. The criteria for voltage boosting and impedance matching, that are essential in the operation of energy harvester under low ambient RF levels, as well as the design considerations for a pi-match network to achieve matching to 50 Ohms, are elaborated on. In addition their application is demonstrated through simulations carried out using Advanced Design System (ADS) simulator. Furthermore, measurement results of an already fabricated dual-band RF harvester are presented, and the approach taken to improve the antenna design from the harvester chip measured input impedance is discussed. The integrated antenna-harvester system tested was capable of harvesting ambient RF power and generating DC output voltage levels above 1 V

Lower-order compensation chain threshold-reduction technique for multi-stage voltage multipliers

This paper presents a novel threshold-compensation technique for multi-stage voltage multipliers employed in low power applications such as passive and autonomous wireless sensing nodes (WSNs) powered by energy harvesters. The proposed threshold-reduction technique enables a topological design methodology which, through an optimum control of the trade-off among transistor conductivity and leakage losses, is aimed at maximizing the voltage conversion efficiency (VCE) for a given ac input signal and physical chip area occupation. The conducted simulations positively assert the validity of the proposed design methodology, emphasizing the exploitable design space yielded by the transistor connection scheme in the voltage multiplier chain. An experimental validation and comparison of threshold-compensation techniques was performed, adopting 2N5247 N-channel junction field effect transistors (JFETs) for the realization of the voltage multiplier prototypes. The attained measurements clearly support the effectiveness of the proposed threshold-reduction approach, which can significantly reduce the chip area occupation for a given target output performance and ac input signal