High Efficiency Cross-Coupled Charge Pump Circuit with Four-Clock Signals

© Allerton Press, Inc. 2018A fully integrated cross-coupled charge pump circuit for boosting dc-to-dc converter applications with four-clock signals has been proposed. With the new clock scheme, this charge pump eliminates all of the reversion power loss and reduces the ripple voltage. In addition, the largest voltage differences between the terminals of all transistors do not exceed the power supply voltage for solving the gate-oxide overstress problem in the conventional charge pump circuits and enhancing the reliability. This proposed charge pump circuit does not require any extra level shifter; therefore, the power efficiency is increased. The proposed charge pump circuit has been simulated using Spectre in the TSMC 0.18 μm CMOS process. The simulation results show that the maximum voltage conversion efficiency of the new 3-stage cross-coupled circuit with an input voltage of 1.5Vis 99.8%. According to the comparison results of the conventional pump and the enhanced charge pump proposed, the output ripple voltage has been significantly reduced.Peer reviewe

A robust high-efficiency cross-coupled charge pump circuit without blocking transistors

This document is the Accepted Manuscript version of the following article: Minglin Ma, Xinglong Cai, Yichuang Sun, and Nike George, ‘A robust high-efficiency cross-coupled charge pump circuit without blocking transistors’, Analog Integrated Circuits and Signal Processing, Vol. 95 (3): 395-401, June 2018. Under embargo until 16 March 2019. The final publication is available at Springer via: https://doi.org/10.1007/s10470-018-1149-xA fully integrated cross-coupled charge pump circuit with a new clock scheme has been presented in this paper. The new clock scheme ensures that all NMOS pre-charge transistors are turned off when the voltages of main clock signals are high. Notably, all PMOS transfer transistors will be turned off when the voltages of the main clock signals are low. As a result, the charge pump eliminates all of the reversion power loss and reduces the ripple voltage. The proposed charge pump has a better performance even in scenarios where the main clock signals are mismatched. The proposed charge pump circuit was simulated using spectre in the TSMC 0.18 µm CMOS process. The simulation results show that the proposed charge pump circuit has a high voltage conversion efficiency and low ripple voltage.Peer reviewe

An Evaluation of 2-phase Charge Pump Topologies with Charge Transfer Switches for Green Mobile Technology

The development of charge pumps has been motivated by the power supply requirements of portable electronic devices. Charge pumps are inductorless DC-DC converters that are small size and high integration. The quality of the charge pump greatly depends on the effectiveness of switches to turn on and off at the designated clock phases. However, to date, no analysis has been carried out on the overall performance of charge pumps based on switch components in practice. This work demonstrates the characteristics of transistors as charge transfer switches and their effects on the performance of a charge pump. Three most common charge pump topologies are evaluated in terms of voltage drop due to on-resistance and charge loss per switch. Simulations are performed in 0.35μm Austriamicrosystems (AMS) technology for Dickson, Voltage Doubler and Makowski charge pump topologies in steady and dynamic states. In addition, the effect of switch parameters for different charge pump topologies are compared and analysed. We demonstrate that the Makowski charge pump is the topology for future green mobile technology

Energy- and Area-Efficient DC-DC Converters Fabricated in Low Temperature Crystalline Silicon-on-Glass Technology

The display industry is moving toward the development of system-on-panel (SOP) architectures to make increasingly compact small-format displays and reduce manufacturing cost. Presently, the voltages required by pixel drivers, row scan logic, and timing circuitry, are generated from a single supply voltage using charge pumps fabricated on a high voltage, monolithic integrated circuit mounted off the glass panel. In this work, a new high-efficiency charge pump architecture for fabrication on display glass substrates is presented. The distinguishing feature of this work is the nestedclock timing scheme used to improve power efficiency and reduce output voltage noise without the use of external capacitors. The circuit is intended for implementation on a novel low-temperature crystalline silicon thin-film transistor technology (SiOG) that exhibits superior performance compared to other low-temperature fabrication processes. Based on simulation results, the proposed circuit exhibits both smaller ripple voltage (61% smaller) and improved power efficiency (80.6% vs. 67.8%) when compared to previous work

High-efficiency high voltage hybrid charge pump design with an improved chip area

A hybrid charge pump was developed in a 0.13- $\mu \text{m}$ Bipolar-CMOS-DMOS (BCD) process which utilised high drain-source voltage MOS devices and low-voltage integrated metal-insulator-metal (MIM) capacitors. The design consisted of a zero-reversion loss cross-coupled stage and a new self-biased serial-parallel charge pump design. The latter has been shown to have an area reduction of 60% in comparison to a Schottky diode-based Dickson charge pump operating at the same frequency. Post-layout simulations were carried out which demonstrated a peak efficiency of 38% at the output voltage of 18.5 V; the maximum specified output voltage of 27 V was also achieved. A standalone serial-parallel charge pump was shown to have a better transient response and a flatter efficiency curve; these are preferable for time-sensitive applications with a requirement of a broader range of output currents. These findings have significant implications for reducing the total area of implantable high-voltage devices without sacrificing charge pump efficiency or maximum output voltage

A High Efficiency and Low Ripple Cross-Coupled Charge Pump Circuit

A fully integrated cross-coupled charge pump circuit with four-clock signals and a new method of body bias have been proposed. The new clock scheme eliminates all of the reversion power loss and reduces the ripple voltage. In addition, the largest voltage differences between the terminals of all transistors do not exceed the supply voltage. We have also solved the gate-oxide overstress problem in the conventional charge pump circuits and enhanced the reliability. The proposed charge pump circuit has been simulated using Spectre and in the TSMC 0.18um CMOS process. The simulation results show that the maximum voltage conversion efficiency of the new 3-stage cross-coupled circuit with an input voltage of 1.5V is 99.8%. Moreover, the output ripple voltage has been significantly reduced.Peer reviewe

Energy-Efficient Start-up Power Management for Batteryless Biomedical Implant Devices

This paper presents a solar energy harvesting power management using the high-efficiency switched capacitor DC-DC converter for biomedical implant applications. By employing an on-chip start-up circuit with parallel connected Photovoltaic (PV) cells, a small efficiency improvement can be obtained when compared with the traditional stacked photodiode methodology to boost the harvested voltage while preserving a single-chip solution. The PV cells have been optimised in the PC1D software and the optimal parameters modelled in the Cadence environment. A cross-coupled circuit with level shifter loop is also proposed to improve the overall step up voltage output and hybrid converter increases the start-up speed by 23.5%. The proposed system is implemented in a standard 0.18-μm CMOS technology. Simulation results show that the 4-phase start-up and cross coupled with level-shifter can achieve a maximum efficiency of 60%

Energy-Efficient Start-up Power Management for Batteryless Biomedical Implant Devices

This paper presents a solar energy harvesting power management using the high-efficiency switched capacitor DC-DC converter for biomedical implant applications. By employing an on-chip start-up circuit with parallel connected Photovoltaic (PV) cells, a small efficiency improvement can be obtained when compared with the traditional stacked photodiode methodology to boost the harvested voltage while preserving a single-chip solution. The PV cells have been optimised in the PC1D software and the optimal parameters modelled in the Cadence environment. A cross-coupled circuit with level shifter loop is also proposed to improve the overall step up voltage output and hybrid converter increases the start-up speed by 23.5%. The proposed system is implemented in a standard 0.18-μm CMOS technology. Simulation results show that the 4-phase start-up and cross coupled with level-shifter can achieve a maximum efficiency of 60%

A Charge Pump Architecture with High Power-Efficiency and Low Output Ripple Noise in 0.5 μm CMOS Process Technology

The demand of portable consumer electronic devices is skyrocketing day-by-day. Such modern integrated microsystems have several functional blocks which require different voltages to operate adequately. DC-DC converter circuits are used to generate different voltage domains for different functional blocks on large integrated microsystems from a single voltage battery-operated power supply. Charge pump is an inductorless DC-DC converter which generates higher positive voltage or lower voltage or negative voltage from the applied reference voltage. A charge pump circuit uses switches for charge transfer action and capacitors for charge storage. The thesis presents a high power-efficiency charge pump architecture with low output ripple noise in the AMI N-well 0.5 µm CMOS process technology. The switching action of the proposed charge pump architecture is controlled by a dual phase non-overlapping clock system. In order to achieve high power-efficiency, the power losses due to the leakage currents, the finite switch resistance and the imperfect charge transfer between the capacitors are taken into consideration and are minimized by proper switching of the charge transfer switches and by using different auxiliary circuits. To achieve low output ripple noise, the continuous current pumping method is proposed and implemented in the charge pump architecture. The proposed charge pump can operate over the wide input voltage range varying from 3 V to 7 V with the power conversion efficiency of 90%. The loading current drive capability of the proposed charge pump is ranging from 0 to 45 mA. The worst case output ripple voltage is less than 25 mV. To prove the concept, the design of the proposed charge pump is simulated rigorously over different process, temperature and voltage corners

High Voltage Energy Harvesters

Green energy helps in reducing carbon emission from fossil fuel, harvesting energy from natural resources like wind to power consumer appliances. To date, many researches have been focusing on designing circuits that harvest energy from electromagnetic signals wirelessly. While it could be designed to be efficient, the generated power however is insufficient to drive large loads. Wind energy is highly available environmentally but development of small-scale energy harvesting apparatus aiming to extract significant power from miniature brushless fan has received limited attention. The aim of this chapter is to give audience an insight of different voltage multipliers used in energy harvester and knowledge on various circuit techniques to configure voltage multipliers for use in different high voltage applications. These include AC-DC converter, AC-AC converter and variable AC-DC converter