Extended Bandwidth Doherty Power Amplifier for Carrier Aggregated Signals

In the conventional classes of power amplifiers the efficiency drops at power back-off, whereas in order to maximize the spectral efficiency and data rate, wireless communication standards employ signals with high peak to average power ratio. This results in low average efficiency for power amplifiers, which in turn results in heavy cooling requirements and damage to the environment. To improve the low back-off efficiency Doherty technique has been widely investigated. But, the conventional Doherty power amplifiers are fairly narrowband, while modern transmitters are needed to support multiple standards and operate at multiple frequency bands. This thesis proposes two novel output combiners for Doherty power amplifiers with extended bandwidth. It will be shown analytically how the problem of wideband Doherty can be converted into an impedance synthesization problem. Then two networks to synthesize the desired impedance are proposed. To achieve the proper load modulation over a wide bandwidth, the first proposed combiner employs a quarter-wave short-circuited stub at the output of the peaking transistor and the second proposed combiner uses a parallel LC tank at the same node. In addition to inherent wideband characteristics, the proposed Doherty output combiners have three other important benefits. First, they present small low-frequency impedance for both the main and peaking transistors, which results in improved linearity and linearizability when the amplifier is concurrently driven with multi-band modulated signals. Second, the new combiners result in smaller group delay variation across the band compared to the conventional Doherty amplifier, which results in improved linearizability when the amplifier is driven with extra wideband modulated signals. Finally, the output capacitance of the peaking transistor can be easily absorbed into the combiners without compromising the performance of the amplifier. The thesis starts with an overview of the Doherty power amplifier principles and provides a bandwidth analysis for the conventional Doherty power amplifier. Then it continues with the new approach to extend the bandwidth of Doherty amplifiers with respect to requirements of multi-band transmission. Based on the proposed combiners, two Gallium Nitride 20 W Doherty power amplifiers have been designed and fabricated. The measurement results have been provided to validate the developed theory. The first amplifier covers 1.72 to 2.27 GHz and the second one covers 700 to 950 MHz and both maintain higher than 48 % of drain efficiency at 6 dB back-off across the band. The two amplifiers are successfully linearized when driven with carrier aggregated modulated signals

A Scalable 6-to-18 GHz Concurrent Dual-Band Quad-Beam Phased-Array Receiver in CMOS

This paper reports a 6-to-18 GHz integrated phased- array receiver implemented in 130-nm CMOS. The receiver is easily scalable to build a very large-scale phased-array system. It concurrently forms four independent beams at two different frequencies from 6 to 18 GHz. The nominal conversion gain of the receiver ranges from 16 to 24 dB over the entire band while the worst-case cross-band and cross-polarization rejections are achieved 48 dB and 63 dB, respectively. Phase shifting is performed in the LO path by a digital phase rotator with the worst-case RMS phase error and amplitude variation of 0.5° and 0.4 dB, respectively, over the entire band. A four-element phased-array receiver system is implemented based on four receiver chips. The measured array patterns agree well with the theoretical ones with a peak-to-null ratio of over 21.5 dB

Distributed active transformer - a new power-combining andimpedance-transformation technique

In this paper, we compare the performance of the newly introduced distributed active transformer (DAT) structure to that of conventional on-chip impedance-transformations methods. Their fundamental power-efficiency limitations in the design of high-power fully integrated amplifiers in standard silicon process technologies are analyzed. The DAT is demonstrated to be an efficient impedance-transformation and power-combining method, which combines several low-voltage push-pull amplifiers in series by magnetic coupling. To demonstrate the validity of the new concept, a 2.4-GHz 1.9-W 2-V fully integrated power-amplifier achieving a power-added efficiency of 41% with 50-Ω input and output matching has been fabricated using 0.35-μm CMOS transistor

Work and energy gain of heat-pumped quantized amplifiers

We investigate heat-pumped single-mode amplifiers of quantized fields in high-Q cavities based on non-inverted two-level systems. Their power generation is shown to crucially depend on the capacity of the quantum state of the field to accumulate useful work. By contrast, the energy gain of the field is shown to be insensitive to its quantum state. Analogies and differences with masers are explored

Photoelectrochemical ion concentration polarization : a microfluidic ion filtration system using light-driven electrochemical reactions

We report an ion separation or filtration method used in microchannel called photoelectrochemical ion concentration polarization (pICP). As a variant of faradaic ion concentration polarization (fICP), pICP utilizes TiO₂ photoelectrochemistry to form an ion depletion zone (IDZ) with light. A microfluidic device with TiO₂ photoanode and Pt cathode generated IDZ near the cathode by generating a corresponding electrochemical reaction. Local electric field near the cathode was amplified with TiO₂ irradiation. Furthermore, on-chip solution conductivity measurement confirmed decrease in ion concentration as a consequence of pICP ion filtration.Chemistr

Improving DRAM Performance by Parallelizing Refreshes with Accesses

Modern DRAM cells are periodically refreshed to prevent data loss due to leakage. Commodity DDR DRAM refreshes cells at the rank level. This degrades performance significantly because it prevents an entire rank from serving memory requests while being refreshed. DRAM designed for mobile platforms, LPDDR DRAM, supports an enhanced mode, called per-bank refresh, that refreshes cells at the bank level. This enables a bank to be accessed while another in the same rank is being refreshed, alleviating part of the negative performance impact of refreshes. However, there are two shortcomings of per-bank refresh. First, the per-bank refresh scheduling scheme does not exploit the full potential of overlapping refreshes with accesses across banks because it restricts the banks to be refreshed in a sequential round-robin order. Second, accesses to a bank that is being refreshed have to wait. To mitigate the negative performance impact of DRAM refresh, we propose two complementary mechanisms, DARP (Dynamic Access Refresh Parallelization) and SARP (Subarray Access Refresh Parallelization). The goal is to address the drawbacks of per-bank refresh by building more efficient techniques to parallelize refreshes and accesses within DRAM. First, instead of issuing per-bank refreshes in a round-robin order, DARP issues per-bank refreshes to idle banks in an out-of-order manner. Furthermore, DARP schedules refreshes during intervals when a batch of writes are draining to DRAM. Second, SARP exploits the existence of mostly-independent subarrays within a bank. With minor modifications to DRAM organization, it allows a bank to serve memory accesses to an idle subarray while another subarray is being refreshed. Extensive evaluations show that our mechanisms improve system performance and energy efficiency compared to state-of-the-art refresh policies and the benefit increases as DRAM density increases.Comment: The original paper published in the International Symposium on High-Performance Computer Architecture (HPCA) contains an error. The arxiv version has an erratum that describes the error and the fix for i

Baseband analog front-end and digital back-end for reconfigurable multi-standard terminals

Multimedia applications are driving wireless network operators to add high-speed data services such as Edge (E-GPRS), WCDMA (UMTS) and WLAN (IEEE 802.11a,b,g) to the existing GSM network. This creates the need for multi-mode cellular handsets that support a wide range of communication standards, each with a different RF frequency, signal bandwidth, modulation scheme etc. This in turn generates several design challenges for the analog and digital building blocks of the physical layer. In addition to the above-mentioned protocols, mobile devices often include Bluetooth, GPS, FM-radio and TV services that can work concurrently with data and voice communication. Multi-mode, multi-band, and multi-standard mobile terminals must satisfy all these different requirements. Sharing and/or switching transceiver building blocks in these handsets is mandatory in order to extend battery life and/or reduce cost. Only adaptive circuits that are able to reconfigure themselves within the handover time can meet the design requirements of a single receiver or transmitter covering all the different standards while ensuring seamless inter-interoperability. This paper presents analog and digital base-band circuits that are able to support GSM (with Edge), WCDMA (UMTS), WLAN and Bluetooth using reconfigurable building blocks. The blocks can trade off power consumption for performance on the fly, depending on the standard to be supported and the required QoS (Quality of Service) leve

The 1982 ASEE-NASA Faculty Fellowship program (Aeronautics and Research)

The NASA/ASEE Summer Faculty Fellowship Program (Aeronautics and Research) conducted at the NASA Goddard Space Flight Center during the summer of 1982 is described. Abstracts of the Final Reports submitted by the Fellows detailing the results of their research are also presented