Optoelectronic devices for power conservation and generation

Energy conservation and generation have become increasingly important in society. Here, we pursue novel transistor technologies based on three-dimensional (3D) FinFETs and two-dimensional (2D) materials to make low power, high speed transistors. We also develop quasi-2D silicon thin film solar cells for power generation. First, a novel approach of doping III-V semiconductors is presented. Oxygen rich silicon oxide (SiO [subscript x], where x > 2) is found to behave as a solid dopant source when deposited on InGaAs, followed by thermal annealing. Oxygen, when diffused into InGaAs, act as n-type dopants where the active carrier concentration reaches up to 1.4 x 10¹⁸ cm³. Besides the simple, CMOS compatible doping technique of solid source doping, another interesting factor is the dopant concentration can be altered by the deposited dopant thickness, which adds an additional control knob therefore allowing enhanced control over the doping process. Thermally induced compressive stress within InGaAs due to the difference in coefficient of thermal expansion (CTE) between InGaAs and SiO [subscript x] is known to increase the number of vacancies within InGaAs therefore giving rise to active dopant concentration. This approach can be used to make high speed, low power transistors. Second, study of thin indium metal contacts on InGaAs is presented. Unlike silicon, III-V compound semiconductors such as InGaAs decomposes around 450 ˚C which result in out-diffusion of indium and gallium and decrease in metal-InGaAs contact resistance. By adding a thin layer of indium between the metal-InGaAs interface, the out-diffusion of gallium was minimized. Third, solar cells based on graphene-silicon (GS) heterojunction architecture are demonstrated on bendable crystalline silicon substrates. Flexible, thin silicon films are fabricated by using the thermal expansion difference between electroplated nickel and bulk silicon, which generates residual strain upon thermal cycling. By controlling the amount of thermal stress, silicon thicknesses between 8 and 35 µm are exfoliated through a kerf-less mechanical method. Together with multi-layer graphene (MLG) grown by chemical vapor deposition (CVD) and atomic layer deposition (ALD) of Al₂O₃ as a silicon passivation layer, power conversion efficiencies (PCE) of 7.4 % were achieved on bendable silicon substrates. Finally, Chapter 7 summarizes the all the chapters from this dissertation and some thoughts for future work.Electrical and Computer Engineerin

Modelling and simulation study of NMOS Si nanowire transistors

Nanowire transistors (NWTs) represent a potential alternative to Silicon FinFET technology in the 5nm CMOS technology generation and beyond. Their gate length can be scaled beyond the limitations of FinFET gate length scaling to maintain superior off-state leakage current and performance thanks to better electrostatic control through the semiconductor nanowire channels by gate-all-around (GAA) architecture. Furthermore, it is possible to stack nanowires to enhance the drive current per footprint. Based on these considerations, vertically-stacked lateral NWTs have been included in the latest edition of the International Technology Roadmap for Semiconductors (ITRS) to allow for further performance enhancement and gate pitch scaling, which are key criteria of merit for the new CMOS technology generation. However, electrostatic confinement and the transport behaviour in these devices are more complex, especially in or beyond the 5nm CMOS technology generation. At the heart of this thesis is the model-based research of aggressively-scaled NWTs suitable for implementation in or beyond the 5nm CMOS technology generation, including their physical and operational limitations and intrinsic parameter fluctuations. The Ensemble Monte Carlo approach with Poisson-Schrödinger (PS) quantum corrections was adopted for the purpose of predictive performance evaluation of NWTs. The ratio of the major to the minor ellipsoidal cross-section axis (cross-sectional aspect ratio - AR) has been identified as a significant contributing factor in device performance. Until now, semiconductor industry players have carried out experimental research on NWTs with two different cross-sections: circular cylinder (or elliptical) NWTs and nanosheet (or nanoslab) NWTs. Each version has its own benefits and drawbacks; however, the key difference between these two versions is the cross-sectional AR. Several critical design questions, including the optimal NWT cross-sectional aspect ratio, remain unanswered. To answer these questions, the AR of a GAA NWT has been investigated in detail in this research maintaining the cross-sectional area constant. Signatures of isotropic charge distributions within Si NWTs were observed, exhibiting the same attributes as the golden ratio (Phi), the significance of which is well-known in the fields of art and architecture. To address the gap in the existing literature, which largely explores NWT scaling using single-channel simulation, thorough simulations of multiple channels vertically-stacked NWTs have been carried out with different cross-sectional shapes and channel lengths. Contact resistance, non-equilibrium transport and quantum confinement effects have been taken into account during the simulations in order to realistically access performance and scalability. Finally, the individual and combined effects of key statistical variability (SV) sources on threshold voltage (VT), subthreshold slope (SS), ON-current (Ion) and drain-induced barrier lowering (DIBL) have been simulated and discussed. The results indicate that the variability of NWTs is impacted by device architecture and dimensions, with a significant reduction in SV found in NWTs with optimal aspect ratios. Furthermore, a reduction in the variability of the threshold voltage has been observed in vertically-stacked NWTs due to the cancelling-out of variability in double and triple lateral channel NWTs

Development of a fully-depleted thin-body FinFET process

The goal of this work is to develop the processes needed for the demonstration of a fully-depleted (FD) thin-body fin field effect transistor (FinFET). Recognized by the 2003 International Technology Roadmap for Semiconductors as an emerging non-classical CMOS technology, FinFETs exhibit high drive current, reduced short-channel effects, an extreme scalability to deep submicron regimes. The approach used in this study will build on previous FinFET research, along with new concepts and technologies. The critical aspects of this research are: (1) thin body creation using spacer etchmasks and oxidation/etchback schemes, (2) use of an oxynitride gate dielectric, (3) silicon crystal orientation effect evaluation, and (4) creation of fully-depleted FinFET devices of submicron gate length on Silicon-on-Insulator (SOI) substrates. The developed process yielded functional FinFETs of both thin body and wide body variety. Electrical tests were employed to describe device behaviour, including their subthreshold characteristics, standard operation, effects of gate misalignment on device performance, and impact of crystal orientation on device drive current. The process is shown to have potential for deep submicron regimes of fin width and gate length, and provides a good foundation for further research of FinFETs and similar technologies at RIT

Fabrication and characterization of nanoscale dopant devices in silicon

Semiconductor nanostructures consisting of areas of buried dopant atom(s) are crucial com- ponents for present and future complementary metal-oxide-semiconductor (CMOS) transistor technologies as well as for emerging quantum computing architectures. This thesis describes electrically contacted nanoscale devices of buried phosphorus in silicon, fabricated using scanning tunnelling microscope (STM) based hydrogen resist lithography, and char- acterised using scanning microwave microscopy (SMM). The goal is to improve nanoscale device fabrication strategies and develop methods that allow a direct device characterisation for a broad range of applications such as the fabrication of a silicon quantum computer. At first, a step by step guide for the fabrication strategy that has been developed is presented. The resulting nanoscale devices, consisting of a single layer of phosphorus atoms in silicon (so called δ-layers), are characterised by electrical transport measurements and SMM. The transport measurements enable the study of the sensitivity of conduction to small changes in dopant densities and the determination of the δ-layer ’electronic width’, along with the growth quality of the δ -layers. The second part of the thesis describes the development of a characterisation scheme using SMM that not only enables us to non-destructively image atomically-thin patterned nanostructures buried in silicon, but also extract quantitative parameters such as depth and conductance. This scheme was subsequently applied to extract similar parameters from a three-dimensional (3D) sample, whose complexity and difficulty of fabrication far exceeds any other published 3D P-in-Si structure made using hydrogen resist lithography. We also demonstrate that SMM spectroscopy in conjunction with finite element modelling can be employed to identify the contributions to the measured SMM complex admittance that orig- inate from the substrate, the patterned δ-layer region and the two-dimensional (2D) nature of the two-dimensional electron gas (2DEG). Finally, characterisation is performed on an active P-in-Si patterned device component in the form of a 1μm×10μm wire with an in-plane bias applied along the wire. The full range of scanning probe capabilities of an SMM setup is applied for characterisation, including Kelvin probe force microscope (KPFM) and scanning capacitance force microscope (SCFM)

An Integrated BiCMOS driver chip for medium power applications

The development of an integrated driver circuit intended for medium power switching applications is presented. The device contains, on one chip, CMOS digital control logic and bipolar drivers, with BiCMOS interface between the two technologies. The custom integrated circuit includes four outputs each capable of switching over 500 mA at 30 volts, at a frequency of up to 1 MHz. The development effort includes the design of the chip with its component circuits and cells. Standard cell CMOS logic gates along with drive and interface circuits were designed and characterized. An appropriate BiCMOS process was developed which utilizes an n-well based 4-micron polysilicon gate MOS technology and vertical NPNs with subcollector and double emitter implants. The chip performance specifications are evaluated with respect to technology requirements and device characteristics, and trade-offs in the design of the chip and the process are examined. Process and device modeling results are compared with the measured data, which show that the objectives of the design are successfully met for the various applications involving resistive, capacitive, and inductive loads

Electrical characterization and modeling of low dimensional nanostructure FET

At the beginning of this thesis, basic and advanced device fabrication process which I haveexperienced during study such as top-down and bottom-up approach for the nanoscale devicefabrication technique have been described. Especially, lithography technology has beenfocused because it is base of the modern device fabrication. For the advanced device structure,etching technique has been investigated in detail.The characterization of FET has been introduced. For the practical consideration in theadvanced FET, several parameter extraction techniques have been introduced such as Yfunction,split C-V etc.FinFET is one of promising alternatives against conventional planar devices. Problem ofFinFET is surface roughness. During the fabrication, the etching process induces surfaceroughness on the sidewall surfaces. Surface roughness of channel decreases the effectivemobility by surface roughness scattering. With the low temperature measurement andmobility analysis, drain current through sidewall and top surface was separated. From theseparated currents, effective mobilities were extracted in each temperature conditions. Astemperature lowering, mobility behaviors from the transport on each surface have differenttemperature dependence. Especially, in n-type FinFET, the sidewall mobility has strongerdegradation in high gate electric field compare to top surface. Quantification of surfaceroughness was also compared between sidewall and top surface. Low temperaturemeasurement is nondestructive characterization method. Therefore this study can be a propersurface roughness measurement technique for the performance optimization of FinFET.As another quasi-1 D nanowire structure device, 3D stacked SiGe nanowire has beenintroduced. Important of strain engineering has been known for the effective mobility booster.The limitation of dopant diffusion by strain has been shown. Without strain, SiGe nanowireFET showed huge short channel effect. Subthreshold current was bigger than strained SiGechannel. Temperature dependent mobility behavior in short channel unstrained device wascompletely different from the other cases. Impurity scattering was dominant in short channelunstrained SiGe nanowire FET. Thus, it could be concluded that the strain engineering is notnecessary only for the mobility booster but also short channel effect immunity.Junctionless FET is very recently developed device compare to the others. Like as JFET,junctionless FET has volume conduction. Thus, it is less affected by interface states.Junctionless FET also has good short channel effect immunity because off-state ofjunctionless FET is dominated pinch-off of channel depletion. For this, junctionless FETshould have thin body thickness. Therefore, multi gate nanowire structure is proper to makejunctionless FET.Because of the surface area to volume ratio, quasi-1D nanowire structure is good for thesensor application. Nanowire structure has been investigated as a sensor. Using numericalsimulation, generation-recombination noise property was considered in nanowire sensor.Even though the surface area to volume ration is enhanced in the nanowire channel, devicehas sensing limitation by noise. The generation-recombination noise depended on the channelgeometry. As a design tool of nanowire sensor, noise simulation should be carried out toescape from the noise limitation in advance.The basic principles of device simulation have been discussed. Finite difference method andMonte Carlo simulation technique have been introduced for the comprehension of devicesimulation. Practical device simulation data have been shown for examples such as FinFET,strongly disordered 1D channel, OLED and E-paper.At the beginning of this thesis, basic and advanced device fabrication process which I haveexperienced during study such as top-down and bottom-up approach for the nanoscale devicefabrication technique have been described. Especially, lithography technology has beenfocused because it is base of the modern device fabrication. For the advanced device structure,etching technique has been investigated in detail.The characterization of FET has been introduced. For the practical consideration in theadvanced FET, several parameter extraction techniques have been introduced such as Yfunction,split C-V etc.FinFET is one of promising alternatives against conventional planar devices. Problem ofFinFET is surface roughness. During the fabrication, the etching process induces surfaceroughness on the sidewall surfaces. Surface roughness of channel decreases the effectivemobility by surface roughness scattering. With the low temperature measurement andmobility analysis, drain current through sidewall and top surface was separated. From theseparated currents, effective mobilities were extracted in each temperature conditions. Astemperature lowering, mobility behaviors from the transport on each surface have differenttemperature dependence. Especially, in n-type FinFET, the sidewall mobility has strongerdegradation in high gate electric field compare to top surface. Quantification of surfaceroughness was also compared between sidewall and top surface. Low temperaturemeasurement is nondestructive characterization method. Therefore this study can be a propersurface roughness measurement technique for the performance optimization of FinFET.As another quasi-1 D nanowire structure device, 3D stacked SiGe nanowire has beenintroduced. Important of strain engineering has been known for the effective mobility booster.The limitation of dopant diffusion by strain has been shown. Without strain, SiGe nanowireFET showed huge short channel effect. Subthreshold current was bigger than strained SiGechannel. Temperature dependent mobility behavior in short channel unstrained device wascompletely different from the other cases. Impurity scattering was dominant in short channelunstrained SiGe nanowire FET. Thus, it could be concluded that the strain engineering is notnecessary only for the mobility booster but also short channel effect immunity.Junctionless FET is very recently developed device compare to the others. Like as JFET,junctionless FET has volume conduction. Thus, it is less affected by interface states.Junctionless FET also has good short channel effect immunity because off-state ofjunctionless FET is dominated pinch-off of channel depletion. For this, junctionless FETshould have thin body thickness. Therefore, multi gate nanowire structure is proper to makejunctionless FET.Because of the surface area to volume ratio, quasi-1D nanowire structure is good for thesensor application. Nanowire structure has been investigated as a sensor. Using numericalsimulation, generation-recombination noise property was considered in nanowire sensor.Even though the surface area to volume ration is enhanced in the nanowire channel, devicehas sensing limitation by noise. The generation-recombination noise depended on the channelgeometry. As a design tool of nanowire sensor, noise simulation should be carried out toescape from the noise limitation in advance.The basic principles of device simulation have been discussed. Finite difference method andMonte Carlo simulation technique have been introduced for the comprehension of devicesimulation. Practical device simulation data have been shown for examples such as FinFET,strongly disordered 1D channel, OLED and E-paper.SAVOIE-SCD - Bib.électronique (730659901) / SudocGRENOBLE1/INP-Bib.électronique (384210012) / SudocGRENOBLE2/3-Bib.électronique (384219901) / SudocSudocFranceF

Power Semiconductors for An Energy-Wise Society

This IEC White Paper establishes the critical role that power semiconductors play in transitioning to an energy wise society. It takes an in-depth look at expected trends and opportunities, as well as the challenges surrounding the power semiconductors industry. Among the significant challenges mentioned is the need for change in industry practices when transitioning from linear to circular economies and the shortage of skilled personnel required for power semiconductor development. The white paper also stresses the need for strategic actions at the policy-making level to address these concerns and calls for stronger government commitment, policies and funding to advance power semiconductor technologies and integration. It further highlights the pivotal role of standards in removing technical risks, increasing product quality and enabling faster market acceptance. Besides noting benefits of existing standards in accelerating market growth, the paper also identifies the current standardization gaps. The white paper emphasizes the importance of ensuring a robust supply chain for power semiconductors to prevent supply-chain disruptions like those seen during the COVID-19 pandemic, which can have widespread economic impacts.The white paper highlights the importance of inspiring young professionals to take an interest in power semiconductors and power electronics, highlighting the potential to make a positive impact on the world through these technologies.The white paper concludes with recommendations for policymakers, regulators, industry and other IEC stakeholders for collaborative structures and accelerating the development and adoption of standards

Analysis of design strategies for RF ESD problems in CMOS circuits

This thesis analyses the design strategies used to protect RF circuits that are implemented in CMOS technologies. It investigates, in detail, the physical mechanisms involved when a ggNMOS structure is exposed to an ESD event and undergoes snapback. The understanding gained is used to understand why the performance of the current RF ESD clamp is poor and suggestions are made as to how the performance of ggNMOS clamps can be improved beyond the current body of knowledge. The ultimate aim is to be able to design effective ESD protection clamps whilst minimising the effect the circuit has on RF I/O signals. A current ggNMOS based RF ESD I/O protection circuit is analysed in detail using a Transmission Line Pulse (TLP) tester. This is shown to be a very effective diagnostic tool by showing many characteristics of the ggNMOS during the triggering and conducting phase of the ESD event and demonstrate deficiencies in the clamp design. The use of a FIB enhances the analysis by allowing the isolation of individual components in the circuit and therefore their analysis using the TLP tester. SPICE simulations are used to provide further commentary on the debate surrounding the specification required of a TLP tester for there to be a good correlation between a TLP test and the industry standard Human Body Model (HBM) ESD test. Finite element simulations are used to probe deeper in to the mechanisms involved when a ggNMOS undergoes snapback especially with regard to the contribution parasitic components within the ggNMOS make to the snapback process. New ggNMOS clamps are proposed which after some modification are shown to work. Some of the finite element experiments are repeated in a 0.18μπ7. process CMOS test chip and a comparison is made between the two sets of results. In the concluding chapter understanding that has been gained from previous chapters is combined with the published body of knowledge to suggest and explain improvements in the design of a ggNMOS for RF and standard applications. These improvements will improve homogeneity of ggNMOS operation thus allowing the device size to be reduced and parasitic loading for a given ESD performance. These techniques can also be used to ensure that the ESD current does not take an unintended path through the chip

The characterisation of performance limiting defects in 4H-SiC devices using density functional theory

This thesis is focused on the atomistic modelling of defects both within silicon carbide (SiC) and at the interface between SiC and silicon dioxide (SiO2). These defects are discussed and compared to available experimental data to allow for the identification of performance limiting defects in the current and next generation of 4H-SiC metal oxide semiconductor (MOS) devices. The results presented throughout this thesis are calculated in the 4H-SiC polytype, which is the most relevant polytype for electronic applications, and as such the devices of interest. These simple bulk models were developed and adapted to produce model 4H-SiC / SiO2 interface systems. All the models used were tested and calibrated against the available experimental and theoretical data to ensure they were representative of the device regions of interest. Through the application of density functional theory (DFT) and the models outlined above, defects, both intrinsic and extrinsic, were calculated, allowing for a comparison with electrically detected magnetic resonance (EDMR) measurements to be made. EDMR and to a lesser extent EPR provide a powerful tool for defect identification, providing a magnetic, symmetric and atomistic picture of a defect from a single technique. This allowed the dominant recombination defect in N-implanted pn-junctions to be identified as the neutral NCVSi, giving atomistic meaning to the unidentified signal from N-implanted devices. The effect of the anneal on forming this and other defects is described, allowing the accumulation and observation of the NCVSi to be understood. Without this mechanistic understanding, it was impossible to explain how the NCVSi is able to persist into the fully processed devices when thermodynamically more stable defects did not. Before these calculations could be conducted, an interface model that was appropriate for the devices of interest was required. This was achieved through the comparison of electron energy loss spectroscopy (EELS) and DFT calculations, allowing an interface that is abrupt, but stepped, to be described. Using this model, the combination of EDMR and DFT calculations was then applied to the problem of defect identification at the SiC / SiO2 interface. This approach allowed the PbC (and dual-PbC) to be identified as the dominant interface defect in the current generation of devices. These results provide an atomistic meaning to the experimentally observed signals, allowing the defects linked to the suboptimal device performance to be identified. This makes it possible to envisage a design paradigm to based upon the knowledge of the target defect, and the processes by which they form, guiding and enhancing the synthetic approach. Ultimately, this approach has the potential to allow SiC (and any other material it is applied to) to reach its full technological potential

Variability-Aware Design of Static Random Access Memory Bit-Cell

The increasing integration of functional blocks in today's integrated circuit designs necessitates a large embedded memory for data manipulation and storage. The most often used embedded memory is the Static Random Access Memory (SRAM), with a six transistor memory bit-cell. Currently, memories occupy more than 50% of the chip area and this percentage is only expected to increase in future. Therefore, for the silicon vendors, it is critical that the memory units yield well, to enable an overall high yield of the chip. The increasing memory density is accompanied by aggressive scaling of the transistor dimensions in the SRAM. Together, these two developments make SRAMs increasingly susceptible to process-parameter variations. As a result, in the current nanometer regime, statistical methods for the design of the SRAM array are pivotal to achieve satisfactory levels of silicon predictability. In this work, a method for the statistical design of the SRAM bit-cell is proposed. Not only does it provide a high yield, but also meets the specifications for the design constraints of stability, successful write, performance, leakage and area. The method consists of an optimization framework, which derives the optimal design parameters; i.e., the widths and lengths of the bit-cell transistors, which provide maximum immunity to the variations in the transistor's geometry and intrinsic threshold voltage fluctuations. The method is employed to obtain optimal designs in the 65nm, 45nm and 32nm technologies for different set of specifications. The optimality of the resultant designs is verified. The resultant optimal bit-cell designs in the 65nm, 45nm and 32nm technologies are analyzed to study the SRAM area and yield trade-offs associated with technology scaling. In order to achieve 50% scaling of the bit-cell area, at every technology node, two ways are proposed. The resultant designs are further investigated to understand, which mode of failure in the bit-cell becomes more dominant with technology scaling. In addition, the impact of voltage scaling on the bit-cell designs is also studied