Low-temperature amorphous oxide semiconductors for thin-film transistors and memristors: physical insights and applications

While amorphous oxides semiconductors (AOS), namely InGaZnO (IGZO), have found market application in the display industry, their disruptive properties permit to envisage for more advanced concepts such as System-on-Panel (SoP) in which AOS devices could be used for addressing (and readout) of sensors and displays, for communication, and even for memory as oxide memristors are candidates for the next-generation memories. This work concerns the application of AOS for these applications considering the low thermal budgets (< 180 °C) required for flexible, low cost and alternative substrates. For maintaining low driving voltages, a sputtered multicomponent/multi-layered high-κ dielectric (Ta2O5+SiO2) was developed for low temperature IGZO TFTs which permitted high performance without sacrificing reliability and stability. Devices’ performance under temperature was investigated and the bias and temperature dependent mobility was modelled and included in TCAD simulation. Even for IGZO compositions yielding very high thermal activation, circuit topologies for counteracting both this and the bias stress effect were suggested. Channel length scaling of the devices was investigated, showing that operation for radio frequency identification (RFID) can be achieved without significant performance deterioration from short channel effects, which are attenuated by the high-κ dielectric, as is shown in TCAD simulation. The applicability of these devices in SoP is then exemplified by suggesting a large area flexible radiation sensing system with on-chip clock-generation, sensor matrix addressing and signal read-out, performed by the IGZO TFTs. Application for paper electronics was also shown, in which TCAD simulation was used to investigate on the unconventional floating gate structure. AOS memristors are also presented, with two distinct operation modes that could be envisaged for data storage or for synaptic applications. Employing typical TFT methodologies and materials, these are ease to integrate in oxide SoP architectures

Interpretation and Regulation of Electronic Defects in IGZO TFTs Through Materials & Processes

The recent rise in the market for consumer electronics has fueled extensive research in the field of display. Thin-Film Transistors (TFTs) are used as active matrix switching devices for flat panel displays such as LCD and OLED. The following investigation involves an amorphous metal-oxide semiconductor that has the potential for improved performance over current technology, while maintaining high manufacturability. Indium-Gallium-Zinc-Oxide (IGZO) is a semiconductor material which is at the onset of commercialization. The low-temperature large-area deposition compatibility of IGZO makes it an attractive technology from a manufacturing standpoint, with an electron mobility that is 10 times higher than current amorphous silicon technology. The stability of IGZO TFTs continues to be a challenge due to the presence of defect states and problems associated with interface passivation. The goal of this dissertation is to further the understanding of the role of defect states in IGZO, and investigate materials and processes needed to regulate defects to the level at which the associated influence on device operation is controlled. The relationships between processes associated with IGZO TFT operation including IGZO sputter deposition, annealing conditions and back-channel passivation are established through process experimentation, materials analysis, electrical characterization, and modeling of electronic properties and transistor behavior. Each of these components has been essential in formulating and testing several hypotheses on the mechanisms involved, and directing efforts towards achieving the goal. Key accomplishments and quantified results are summarized as follows: • XPS analysis identified differences in oxygen vacancies in samples before and after oxidizing ambient annealing at 400 °C, showing a drop in relative integrated area of the O 1s peak from 32% to 19%, which experimentally translates to over a thousand fold decrease in the channel free electron concentration. • Transport behavior at cryogenic temperatures identified variable range hopping as the electron transport mechanism at temperature below 130 K, whereas at temperature greater than 130 K, the current vs temperature response followed an Arrhenius relationship consistent with extended state transport. • Refinement of an IGZO material model for TCAD simulation, which consists of oxygen vacancy donors providing an integrated space charge concentration NVO = +5e15 cm-3, and acceptor-like band-tail states with a total integrated ionized concentration of NTA = -2e18 cm-3. An intrinsic electron mobility was established to be Un = 12.7 cm2/V∙s. • A SPICE-compatible 2D on-state operation model for IGZO TFTs has been developed which includes the integration of drain-impressed deionization of band-tail states and results in a 2D modification of free channel charge. The model provides an exceptional match to measured data and TCAD simulation, with model parameters for channel mobility (Uch = 12 cm2/V∙s) and threshold voltage (VT = 0.14 V) having a close match to TCAD analogs. • TCAD material and device models for bottom-gate and double-gate TFT configurations have been developed which depict the role of defect states on device operation, as well as provide insight and support of a presented hypothesis on DIBL like device behavior associated with back-channel interface trap inhomogeneity. This phenomenon has been named Trap Associated Barrier Lowering (TABL). • A process integration scheme has been developed that includes IGZO back-channel passivation with PECVD SiO2, furnace annealing in O2 at 400 °C, and a thin capping layer of alumina deposited via atomic layer deposition. This process supports device stability when subjected to negative and positive bias stress conditions, and thermal stability up to 140 °C. It also enables TFT operation at short channel lengths (Leff ~ 3 µm) with steep subthreshold characteristics (SS ~ 120 mV/dec). The details of these contributions in the interpretation and regulation of electronic defect states in IGZO TFTs is presented, along with the support of device characteristics that are among the best reported in the literature. Additional material on a complementary technology which utilizes flash-lamp annealing of amorphous silicon will also be described. Flash-Lamp Annealed Polycrystalline Silicon (FLAPS) has realized n-channel and p-channel TFTs with promising results, and may provide an option for future applications with the highest performance demands. IGZO is rapidly emerging as the candidate to replace a-Si:H and address the performance needs of display products produced by large panel manufacturing

High Performance Gallium Tin Zinc Oxide Thin Film Transistors By Rf Magnetron Sputtering

With the growing need for large area display technology and the push for a faster and cheaper alternative to the current amorphous indium gallium zinc oxide (a-IGZO) as the active channel layer for pixel-driven thin film transistors (TFTs) display applications, gallium tin zinc oxide (GSZO) has shown to be a promising candidate due to the similar electronic configuration of Sn4+ and In3+. Post deposition annealing at 450 °C of the films in air was found to lead to a high atomic concentration of Sn4+ in the films as ascertained by x-ray photoelectron spectroscopy, which is one of the prerequisites for improved performance of the device. In this work a systematic and detailed study of GSZO TFTs with the channel annealed at 450°C has been carried out, and different effects have been investigated, including: oxygen flow, deposition contacts, further annealing in different ambients and presence of passivation layer on the TFT performance. The electrical and optical stability of the GSZO TFTs have also been the subject of study. These studies provided a more insight into the role of surface and interface states on the TFT performance and its degradation mechanism under stress. Improved device performance with VON of -3.5 V, ION/IOFF of 108, μFE = 4.36 V-1 s-1, and sub-threshold swing (SS) of 0.38 V/dec has been achieved, which is close to those of industrial standard IGZO TFTs. Thus, this work demonstrates GSZO based TFTs as a promising and viable option to the IGZO TFTs

Indium-Gallium-Zinc Oxide Thin-Film Transistors for Active-Matrix Flat-Panel Displays

Amorphous oxide semiconductors (AOSs) including amorphous InGaZnO (a-IGZO) areexpected to be used as the thin-film semiconducting materials for TFTs in the next-generation ultra-high definition (UHD) active-matrix flat-panel displays (AM-FPDs). a-IGZO TFTs satisfy almost all the requirements for organic light-emitting-diode displays (OLEDs), large and fast liquid crystal displays (LCDs) as well as three-dimensional (3D) displays, which cannot be satisfied using conventional amorphous silicon (a-Si) or polysilicon (poly-Si) TFTs. In particular, a-IGZO TFTs satisfy two significant requirements of the backplane technology: high field-effect mobility and large-area uniformity.In this work, a robust process for fabrication of bottom-gate and top-gate a-IGZO TFTs is presented. An analytical drain current model for a-IGZO TFTs is proposed and its validation is demonstrated through experimental results. The instability mechanisms in a-IGZO TFTs under high current stress is investigated through low-frequency noise measurements. For the first time, the effect of engineered glass surface on the performance and reliability of bottom-gate a-IGZO TFTs is reported. The effect of source and drain metal contacts on electrical properties of a-IGZO TFTs including their effective channel lengths is studied. In particular, a-IGZO TFTs with Molybdenum versus Titanium source and drain electrodes are investigated. Finally, the potential of aluminum substrates for use in flexible display applications is demonstrated by fabrication of high performance a-IGZO TFTs on aluminum substrates and investigation of their stability under high current electrical stress as well as tensile and compressive strain

Amorphous In-Ga-Zn-O Thin-Film Transistors for Next Generation Ultra-High Definition Active-Matrix Liquid Crystal Displays.

Next generation ultra-high definition (UHD) active-matrix flat-panel displays have resolutions of 3840x2160 (4K) or 7680x4320 (8K) pixels shown at 120 Hz. The UHD display is expected to bring about immersive viewing experiences and perceived realness. The amorphous In-Ga-Zn-O (a-IGZO) thin-film transistor (TFT) is a prime candidate to be the backplane technology for UHD active-matrix liquid crystal displays (AM-LCDs) because it simultaneously fulfills two critical requirements: (i) sufficiently high field-effect mobility and (ii) uniform deposition in the amorphous phase over a large area. We have developed a robust a-IGZO density of states (DOS) model based on a combination of experimental results and information available in the literature. The impact of oxygen partial pressure during a-IGZO deposition on TFT electrical properties/instability is studied. Photoluminescence (PL) spectra are measured for a IGZO thin films of different processing conditions to identify the most likely electron-hole recombination. For the first time, we report the PL spectra measured within the a IGZO TFT channel region, and differences before/after bias-temperature stress (BTS) are compared. To evaluate the reliability of a-IGZO TFTs for UHD AM-LCD backplane, we have studied its ac BTS instability using a comprehensive set of conditions including unipolar/bipolar pulses, frequency, duty cycle, and drain biases. The TFT dynamic response, including charging characteristics and feedthrough voltage, are studied within the context of 4K and 8K UHD AM-LCD and are compared with hydrogenated amorphous silicon technology. We show that the a-IGZO TFT is fully capable of supporting 8K UHD at 480 Hz. In addition, it is feasible to reduce a-IGZO TFT feedthrough voltage by controlling for non-abrupt TFT switch-off.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/111526/1/ekyu_1.pd

On improvements in metal oxide based flexible transistors through systematic evaluation of material properties

Thin-film metal oxide (MOx) semiconductors have opened the way to a new generation of electronics based on their unique properties. With mobilities, mu, of up to 80 cm2V-1s-1, metal oxides do not rival crystalline silicon (mu~1000 cm2V-1s-1) for complex applications. But such oxides do have three unique characteristics driving great interest: their mobilities persist in the amorphous form, contrary to the thousandfold drop seen in silicon; they are transparent; and they can be processed at, or near, room temperature. Most work on MOx semiconductors, in particular indium gallium zinc oxide (IGZO), has focused on display applications, where MOx thin-film transistors (TFTs) are used to drive individual pixels, reducing power consumption by blocking less light than alternatives, and allowing smaller pixels due to reduced TFT sizes. Such work has seen great advances in IGZO, but has generally not considered the thermal budget during production. By utilising the low temperature processing possible with MOx, a new world of applications becomes possible: flexible electronics. This work aims to improve the characteristics of TFTs based on amorphous IGZO (a-IGZO) through detailed study of the thin-film structure in relation to functional performance, looking at the material structure of three critical layers in an a-IGZO TFT. A study of optimisation of a dielectric layer of Al2O3, deposited by atomic layer deposition (ALD), is presented. This dielectric, between the a-IGZO and the gate electrode, shows a three-layer substructure in what has previously been regarded as a single homogeneous layer. A study of the insulating Al2O3 buffer layer below the a-IGZO compared the properties of Al2O3 deposited by ALD and sputtering. Sputtered material has a more complex structure than ALD, consisting of multiple sublayers that correlate with the sputtering process. The structure of the two materials is discussed, and the impact on device performance considered. A detailed systematic study of the effects of annealing of a-IGZO shows a strong dependence of the density on both time and temperature. A two mechanism model is proposed which consists of structural relaxation of the amorphous material followed by absorption of oxygen from the environment. Finally, investigation of the influence of the buffer material on the a-IGZO, and the structure of this interface showed little difference in the growth of the a-IGZO, but did reveal some changes in the interface, while a systematic study of annealing effects on the a-IGZO-dielectric interface showed some interesting changes in this structure, both of which are likely to significantly impact the operational characteristics of TFT devices

The Effects Of Deposition Conditions On Rf Sputtered Gallium Tin Zinc Oxide Thin Film Transistors

Thin film transistors (TFTs) were fabricated with a transparent amorphous gallium tin zinc oxide (GSZO) channel layer. GSZO is a promising, low cost replacement for the commonly used indium gallium zinc oxide (IGZO).The transistors were fabricated on Si substrates to optimize performance prior to transferring device production to flexible substrates. This dissertation will address the effects of deposition and post-deposition parameters on the film properties and interface traps. It will also address the parameters’ resultant effects on device performance and stability with the use of various characterization techniques. Film properties were studied using x-ray diffraction (XRD) and transmission measurements to assess the structural and optical properties of the deposited films. X-ray photoelectron spectroscopy (XPS) analysis was performed to determine the surface composition of the channel layer, and correlate the surface properties to the resulting device performance. Enhancement and depletion mode devices were fabricated. TFT performance was evaluated through the current-voltage (I-V) characteristics of the devices under normal, electrically stressed and photo-excited conditions operating conditions. Depletion mode TFTs were produced with drain current (ID)= 10-6 A, threshold voltage (VT)= -3 V, subthreshold swing (SS)= 1.3 V/decade, and on/off current ratio (Ion/off)= 106 when operated in the dark without gate stress. TFTs with 10 sccm oxygen incorporation during deposited and post-deposition annealing at 250 °C exhibits the best performance amongst enhancement mode devices with ID of 10-7A, VT of 3 V SS of 1.33 V / decade, and Ion/off of 106. In addition, a stable RT deposited TFT has been achieved with 2 sccm oxygen incorporation, and 250 °C post deposition annealing temperature, that exhibits a ΔVT as low as ~0.5 V for a 3 hour stress period under a gate bias of 1.2 and 12 V

Bias stability of solution-processed In2O3 thin film transistors

We report the effect of bias stress on the drain current and threshold voltage of n-channel thin-film transistors based on solution processed In2O3 layers. Application of a positive gate bias for variable time-periods led to displacements of the transfer curves in the positive gate bias direction. On switching off the gate bias, the transfer curves returned close to their pre-stress state on a timescale similar to that when the gate bias was switched on. The time dependence of the threshold voltage shift is described well by a stretched-exponential model. The temporal behaviour of the threshold voltage shifts is consistent with charge trapping as the dominant effect, although some defect formation cannot be ruled out

용액 공정 인듐갈륨징크 산화물 박막트랜지스터의 뒷 채널 전위 및 드바이 길이를 고려한 결함구조밀도와 신뢰성에 대한 연구

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2016. 2. 홍용택.차세대 디스플레이 응용의 핵심 소자로 비정질 산화물 반도체 박막 트랜지스터에 대한 관심이 높아지고 있다. 특히 비정질 인듐갈륨징크 산화물 반도체는 전하 이동도와 같은 전기적 특성, 균일도, 그리고 공정 온도 등에서 한계에 있는 기존의 실리콘 기반 박막트랜지스터를 대체할 수 있을 것으로 기대되고 있다. 이와 더불어 공정 비용 감소를 위해 용액 공정 기반의 인듐갈륨징크 산화물 반도체 박막 트랜지스터에 대한 연구도 많이 이루어지고 있다. 하지만 보다 많은 응용을 위해서는 용액 공정 기반 인듐갈륨징크 산화물 박막트랜지스터의 물리적인 성질에 대한 연구가 필요한 상황이다. 또한 뒷 채널 영역의 소자 특성에 대한 영향은 인듐갈륨징크 산화물 반도체 박막트랜지스터의 분석에서 간과되어 왔으나, 채널 특성이 뒷 채널 영역 특성의 영향을 받을 정도로 반도체 층이 얇을 때에는 뒷 채널 영역의 영향을 무시할 수 없게 된다. 일반적으로 용액 공정 인듐갈륨징크 산화물 반도체 박막트랜지스터의 경우 10~20 nm의 매우 얇은 반도체 층을 갖기 때문에 소자를 분석할 때에 뒷 채널 표면의 영향은 고려되어야 한다. 본 학위 논문에서는 용액 공정 인듐갈륨징크 산화물 박막트랜지스터의 결함구조밀도와 같은 소자 물리적 특성과 정전압 스트레스에서의 신뢰성을 뒷 채널 표면 전위와 드바이 길이를 고려하여 연구 하였다. 먼저, 용액 공정 인듐갈륨징크 산화물 박막트랜지스터의 결함구조밀도를 추출하는 방법에 대해 연구하였다. 기존에 발표된 결함구조밀도 추출 방법들은 뒷 채널 표면 전위를 0으로 가정하였다. 이는 인가되는 게이트 전압의 영향을 충분히 차폐할 수 있을 정도로 반도체 층이 두꺼울 때에는 적절한 가정이다. 하지만 반도체 층이 드바이 길이보다 얇은 경우에는 뒷 채널 표면 전위가 게이트 전압에 의해 영향을 받을 수 있다. 용액 공정 기반 인듐갈륨징크 산화물 박막 트랜지스터의 경우 약 10 nm 정도의 매우 얇은 반도체 층으로 인해 뒷 채널의 표면 전위가 게이트 전압에 의해 영향을 받을 수 있기 때문에 이러한 가정은 수정이 필요하다. 따라서 뒷 채널 표면 전위를 0으로 가정하고 있는 기존의 추출 방법들은 정확한 결함구조밀도 추출을 위해 뒷 채널의 표면 전위를 고려하여 수정될 필요가 있다. 게이트 전압에 따른 뒷 채널 표면 전위의 변화는 스캐닝 켈빈 프로브 마이크로스코피로 측정 하였으며 기존의 필드 이펙트 방법을 수정하는 데에 사용 될 수 있도록 모델링 하였다. 뒷 채널 표면 전위를 고려하여 새롭게 수정된 필드 이펙트 방법은 기존의 방법에 비해 측정된 활성화 에너지 데이터와 더 일치하는 결과를 보여주었다. 기존의 추출 방법에서는 결함구조밀도가 실제보다 작은 수준으로 추출되는 반면, 수정된 필드 이펙트 방법 통해 더욱 정확히 용액 공정 기반 인듐갈륨징크 산화물 박막 트랜지스터의 결함구조밀도를 얻을 수 있었다. 개발한 결함구조밀도 추출 모델을 이용하여, 어닐링 온도, 조성 비율, 그리고 인듐갈륨징크 산화물 반도체 층의 두께 등 공정 및 소자 파라미터가 결함구조밀도에 미치는 영향에 대해 연구하였다. 다양한 공정 파라미터에 의한 소자의 전기적 특성 변화에 대해 재료적인 관점에서의 분석은 이루어졌지만, 이를 결함구조밀도와 같은 전기적으로 모델링을 하고 분석하는 것에 대한 연구는 아직 이루어지지 않은 상황이다. 이러한 파라미터들의 변화에 의한 소자의 동작을 정확히 분석하고 예측하기 위해서는 결함구조밀도의 변화 등을 전기적으로 모델링 할 필요가 있다. 어닐링 온도와 조성 비율이 변화함에 따라 결함구조밀도의 상대적으로 딥 레벨에 위치하는 스테이트와 테일 스테이트가 변화하였으며, 엑스선 광전자 분광법 결과와 비교를 통해 상대적으로 딥 레벨에 위치하는 스테이트는 산소 공핍 결합과, 테일 스테이트는 잔여 수산화물 결합과 각각 관련이 있다는 것을 알 수 있었다. 또한 다양한 두께의 반도체 층을 갖는 용액 공정 기반 인듐갈륨징크 산화물 박막트랜지스터의 결함구조밀도를 분석, 비교함으로써 핀홀과 같은 물리적 결함과 불규칙성이 테일 스테이트에 영향을 준다는 것을 알 수 있었다. 이러한 분석을 바탕으로 용액 공정 기반 인듐갈륨징크 산화물 반도체 박막 트랜지스터의 반도체 층 결함의 원인을 나타내는 결함구조밀도 맵을 얻을 수 있었다. 마지막으로, 정전압 스트레스에서의 용액 공정 인듐갈륨징크 산화물 박막트랜지스터의 신뢰성에 대해 연구하였다. 양의 게이트 전압 스트레스에서 문턱 전압은 양의 방향으로 이동하였으며, 진공 증착 기반 인듐갈륨징크 산화물 박막트랜지스터와 비슷한 양상을 보였다. 그러나 음의 전압 스트레스에서는 진공 증착 기반 인듐갈륨징크 산화물 박막트랜지스터와 달리 문턱 전압은 스트레스 시간에 따라 선형적으로 변화하였다. 이러한 열화 현상을 분석하기 위하여, 다른 반도체 층 두께와 드바이 길이를 갖는 소자의 신뢰성 측정, 그리고 흡착된 양 전하 물질이 소자의 전기적 특성에 미치는 영향에 대한 2차원 컴퓨터 시뮬레이션을 수행하였다. 그 결과, 음의 게이트 전압 스트레스에서 문턱전압이 선형적으로 이동하는 열화 현상은 공기 중의 양의 전하를 띄는 물질이 뒷 채널 영역에 흡착하는 것에 의한 것이라는 것을 확인 할 수 있었다.Amorphous metal oxide-based thin film transistors (TFTs) have attracted much attention as a most promising candidate for next generation electronic applications. Especially, amorphous indium gallium zinc oxide (IGZO) TFTs are expected to replace conventional silicon-based TFTs which encounter the limitation of electrical properties such as field-effect mobility, uniformity, and process temperature. In addition, there have been many efforts to fabricate IGZO TFTs using solution process to reduce process cost. However, device physics of solution-processed IGZO TFTs still needs to be investigated for further application. Furthermore, the effect of back channel surface region has been neglected in the analysis of IGZO TFTs. However, the back channel surface effect cannot be ignored when IGZO active layer is very thin, so that channel properties are affected by back channel surface. Therefore, the back channel surface effect needs to be considered in the analysis of solution-processed IGZO TFTs because solution-processed IGZO TFTs generally have very thin active layer, approximately 10~20 nm. In this thesis, device physical properties such as density-of-states (DOS) and reliability under bias stress of solution-processed IGZO TFTs are investigated with consideration of back channel surface potential and Debye length. First, the extraction model is developed to extract accurate DOS of solution-processed IGZO TFTs. In most previously reported DOS extraction methods, back channel surface potential (ΦB) was assumed to be zero. This assumption is appropriate when active layer is sufficiently thick to screen the effect of the applied gate voltage (VGS) on ΦB. On the contrary, ΦB is affected by VGS when active layer is thinner than Debye length. The assumption needs to be modified in the case of solution-processed IGZO TFTs, whose active layer is approximately 10 nm. Therefore, previously reported extraction method, which assumed zero potential at back channel surface, needs to be modified with consideration of ΦB for accurate DOS extraction. The variation of ΦB with VGS was measured by scanning Kelvin probe microscopy (SKPM) and modeled to be used for modification of conventional field-effect method. The modified field-effect method considering ΦB exhibited more consistent activation energy (Ea) extraction result with the measured data than conventional one. Accurate DOS of solution-processed IGZO TFTs was extracted with considering ΦB while conventional one underestimated the defect DOS. Second, the effect of process and device parameters on DOS was investigated with varying annealing temperature (Ta), metallic composition ratio or IGZO active layer thickness (tactive). The DOS of each device was extracted by the developed model. The electrical characteristics variation along with various process parameters has been analyzed in the aspect of material chemistry. However, the effect of those parameters on the electrical model such as DOS has not been studied yet. The electrical modeling such as DOS variation is required to simulate device operation accurately as process parameters change. As Ta and metallic composition ratio changed, the relatively deep and tail states of DOS were changed. By comparing the extracted DOS with x-ray photoelectron spectroscopy (XPS) results, it is found that relatively deep and tail states are related to oxygen vacancy and residual hydroxide in solution-processed IGZO film, respectively. It was also found that physical defects, such as pin-holes, and disorder affected tail states from the extracted DOS analysis of solution-processed IGZO TFTs with various tactive. From the DOS analysis, DOS map of solution-processed IGZO TFTs, which shows origins of relatively deep and tail states, is developed. Finally, the stability of solution-processed IGZO TFTs under constant gate bias stress is investigated. Under positive gate bias stress, the transfer characteristics of solution-processed IGZO TFTs were positively shifted and showed similar behavior compared to vacuum-processed IGZO TFTs. However, different behavior of threshold voltage shift (ΔVth) was observed under negative gate bias stress. The time evolution of ΔVth followed linear function. In order to analyze the reliability under negative gate bias stress, the stability of devices with different tactive and Debye length of IGZO layer was measured and the effect of adsorbed charged species on the electrical characteristics was simulated by 2-dimensional technology computer-aided design simulation. As a result, it is found that linear shift of Vth under negative gate bias stress is attributed to the adsorption of positively charged species on back channel surface region.Chapter 1 Introduction 1 1.1 Recent Flat Panel Display 1 1.2 Dissertation Organization 7 Chapter 2 Review of IGZO TFTs 9 2.1 Oxide Semiconductor for TFT Application 10 2.2 Various Extraction Methods of Density-of-States of TFTs 15 2.3 Process Parameter Variation of IGZO TFTs 24 2.4 Reliability of IGZO TFTs 28 Chapter 3 Development of Modified Field-Effect Method with Consideration of Back ChannelSurface Potential 32 3.1 Introduction 32 3.2 Experiment 35 3.2.1 Fabrication of Solution-Processed IGZO TFTs 35 3.2.2 Device and IGZO Film Characterization 40 3.2.3 Scanning Kelvin Probe Microscopy Measurement 40 3.3 Extraction of Density-of-States (DOS) of Solution-Processed IGZO TFTs with Consideration of Back Channel Surface Potential 43 3.3.1 Temperature-Dependent Electrical Characteristics 43 3.3.2 Back Channel Surface Potential of Solution-Processed IGZO TFTs 48 3.3.3 Modified Field-Effect Method Considering Back Channel Surface Potential 52 3.3.4 DOS Extraction of Solution-Processed IGZO TFTs by Modified Field-Effect Method Considering Back Channel Surface Potential 55 3.3.5 Verification of Assumption of Back Channel Surface Potential 59 3.4 Conclusion 63 Chapter 4 Effect of Process Parameters on DOS of Solution-Processed IGZO TFTs 64 4.1 Introduction 64 4.2 Experiment 66 4.3 Effect of Annealing Temperature on DOS of Solution-Processed IGZO TFTs 68 4.3.1 Device Characteristics 68 4.3.2 DOS Extraction Considering Back Channel Surface Potential and Analysis 77 4.4 Effect of Metallic Composition Ratio on DOS of Solution-Processed IGZO TFTs 84 4.4.1 Device Characteristics 84 4.4.2 DOS Extraction Considering Back Channel Surface Potential and Analysis 91 4.5 Effect of Active Layer Thickness on DOS of Solution-Processed IGZO TFTs 98 4.5.1 Device Characteristics 98 4.5.2 DOS Extraction Considering Back Channel Surface Potential and Analysis 104 4.6 DOS Mapping 110 4.7 Conclusion 112 Chapter 5 Analysis of Stability of Solution-Processed IGZO TFTs under Constant Gate Bias Stress 113 5.1 Introduction 113 5.2 Experiment 115 5.3 Stability under Negative Gate Bias Stress 116 5.4 Stability under Positive Gate Bias Stress 125 5.5 Conclusion 129 Chapter 6 Summary 130 Appendix A Circuit Application of Solution-Processed IGZO TFTs 134 Bibliography 149 초록 158Docto

Yttrium and Scandium in Solution-processed Oxide Electronic Materials.

Large area electronics are critical for many novel applications such as smart windows, wearable electronics and Internet of Things. Among candidate materials, metal oxides have relatively good performance and stability and can be deposited by low-cost solution processes. This thesis explores the roles of rare-earth elements yttrium and scandium in solution-processed metal oxide thin films including semiconducting scandium- or yttrium-doped ZTO, conducting scandium- or yttrium-doped zinc oxide, and insulating yttrium-scandium oxide. Yttrium and scandium can act as oxygen getters and stabilizers, and the use of higher-order alloys can improve film thermal stability and electrical performance. First, thin film transistors (TFTs) are used to characterize undoped ZTO films as a baseline. The device performance of solution-processed ZTO TFTs depends on ink Zn to Sn ratio and annealing temperature, optimized to be 7:3 and 480⁰C, respectively. The optimized ZTO has a shallow donor energy level of 7meV and a steep exponential subgap band tail with a percolation energy of 3meV. Sputtered Mo forms an excellent ohmic contact to solution-processed ZTO with a width-normalized contact resistance of 8.7Ω•cm and a transfer length of 0.34μm, making the technology suitable for future sub-micron channel length devices. Yttrium enhances performance of ZTO TFTs at low concentrations (3at%). High yttrium concentrations slightly improve TFT negative bias illumination stress stability by reducing oxygen vacancy-related defects. Second, the introduction of scandium or yttrium in solution-processed ZnO decreases the conductivity by three orders of magnitude, which is ascribed to formation of insulating structures along grain boundaries. Scandium or yttrium also make the resistivity of ZnO more thickness-dependent than undoped ZnO after forming gas anneal, by causing surface depletion and grain disruptions in the film. Third, solution-processed (YxSc1-x)2O3 insulating alloys have comparable dielectric performance to vacuum deposited (YxSc1-x)2O3, with high breakdown field > 4MV/cm, low leakage current and low dielectric frequency dispersion. Even after 900°C anneals induce crystallization, the alloys maintain a high breakdown field. The yttrium- and scandium- doped solution-processed oxides developed here form a complete suite of electronic materials suitable for fabrication of future large-area electronic devices.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/133324/1/wbhu_1.pd