Thermal & electrical simulation for the development of solid-phase polycrystalline silicon TFTs

Solid phase crystallization (SPC) is a processing technique used for conversion of amorphous silicon (a-Si) to polycrystalline silicon (poly-Si). SPC can potentially be used as an alternative to excimer laser annealing to fabricate the semiconductor layer for thin-film transistors (TFTs) in active-matrix liquid crystal display (AMLCD). It is a technique suitable for large-area applications since it involves easily scalable thermal processes in the form of rapid thermal annealing (RTA) and furnace annealing (FA). The SPC parameter space involves the time and temperature of the FA, and the time, temperature, and number of pulses in the RTA process. In developing new process flows for thin-film transistors (TFTs) using SPC, thermal and electrical device simulation are invaluable tools. Comsol® was utilized to explore this SPC experimental parameter space, and provided important insight on temperature conditions not directly measureable on glass substrates (see Fig. 1). Silvaco\u27s Atlas® was utilized to evaluate the TFT response variables of sub-threshold slope (SS), threshold voltage (VT), and maximum current (Imax). Further, a procedure for fitting TFT device characteristics using Atlas was developed. From this simulation fit (see Fig. 2), theoretical trap state distributions for the semiconducting film can be extracted, as well as the trap state distributions at the oxide-semiconductor interfaces

Thin film engineering for transparent thin film transistors

Zinc oxide (ZnO) and Indium Gallium Zinc Oxide (IGZO) thin films are of interest as oxide semiconductors in thin film transistor (TFT) applications, due to visible light transparency, and low deposition temperature. There is particular interest in ZnO and IGZO based transparent TFT devices fabricated at low temperature on low cost flexible substrates. However, thermal annealing processes are typically required to ensure a good performance, suitable long term stability, and to control the point defects which affect the electrical characteristics. Hence there is interest in post deposition processing techniques, particularly where alternatives to high temperature thermal treatments can be utilised in combination with low temperature substrates. This thesis presents the results of a series of experimental studies as an investigation into photonic (excimer laser) processing of low temperature ZnO and IGZO thin films deposited by RF magnetron sputtering and/or by high target utilisation sputtering (HiTUS), to optimise the microstructure and electrical properties for potential use in thin film electronic applications. ZnO thin films were grown at various deposition parameters by varying oxygen flow rates, RF power, oxygen concentration, and growth temperatures

Characterization of materials and fabrication of active matrix thin film transistor arrays for electrical interfacing of biological materials

Electrical interfacing between semiconductor devices and biological materials has been studied for live cell probing which will make it possible to perform direct electrical sensing of cells. To extend the applicability of extracellular and planar microelectrode arrays, recently vertically aligned nanofibers (VACNFs) have been integrated with micro electrode arrays (MEA) for applications such as cell membrane mimics, gene delivery arrays, neuroelectrochemical interfacing arrays, superhydrophobic switches, and intracellular probes. The main drawback of VACNF-MEA devices are the low density of electrodes and passive addressing approach. In order to increase the number of elements of an MEA and enable both stimulation and recording on the same platform, an actively addressed thin film transistor (TFT) array platform was developed. Active matrix-TFTs are highly functional devices which have been used widely as backplanes in display electronics field over the past few decades.VACNFs were integrated onto the TFT array (TFT-VACNF) as they enhance the electrical sensitivity to the cell relative to standard planar arrays; furthermore, the vertical electrodes provide the potential for intracellular sensing within individual cells. This device platform provides great potential as an advanced microelectrode array for direct cell sensing, probing, and recording with a high electrode density and active addressability. In this study, VACNFs were successfully integrated onto TFT devices to demonstrate a new microelectrode array platform. The materials and processes of the TFT structure were designed to be compatible with the requisite high-temperature (~700°C) and direct current Plasma Enhanced Chemical Vapor Deposition (dc-PECVD) VACNF growth process.To extend the applicability of utilizing these vertical electrodes, this dissertation describes: the characterization and optimization of each layer for the TFT; the fabrication process and issues for active matrix TFT array; the critical device integration issues of VACNFs onto active matrix TFT arrays are elaborated; and the initial and final device characteristics are reported

Flash Lamp Annealed LTPS TFTs with ITO Bottom-Gate Structures

As displays continue to increase in resolution and refresh rate, new materials for thin film transistors (TFTs) are required. Low temperature polycrystalline silicon (LTPS) formed by excimer laser annealing (ELA) has been very successful and has been implemented in small displays, but cost and scalability issues prevent it from entering larger display products. Currently LPTS TFTs are top-gate structures due to manufacturing challenges associated with crystallizing thin film silicon when a thermally conductive gate is under portions and insulating glass under others. Bottom-gate devices offer the benefit of higher breakdown voltage, better dielectric-semiconductor interface quality, and direct access to the back-channel region for interface trap passivation. The ability to fabricate bottom-gate devices would allow for different integration and design schemes and is a prerequisite for double gate structures. Flash lamp annealed (FLA) LTPS is an attractive method to expand the size of displays that use high mobility TFTs due to its scalability and parallel production nature. In this work bottom-gate LTPS TFTs were fabricated via FLA with indium tin oxide (ITO), a transparent conductive oxide, used as the gate electrode. A p-channel TFT with 4 µm channel length crystallized with a FLA energy of 4.4 J/cm2 for 250 µs demonstrated a low-field mobility of 190 cm2/(Vs), a subthreshold slope of 325 mV/dec, on/off state ratio of seven orders of magnitude, and a threshold voltage of -5.4 V. A dielectric failure mechanism was identified that compromised the transistor operation under high drain bias and an alternative dopant introduction techniques were proposed to mitigate this issue. An effect due to the transduction of optical energy from the field to thermal energy under the channel via the gate was observed. Details of the FLA crystallization process, device fabrication, and electrical characteristics will be presented

Chromium Modified Crystallization of Silicon Thin Films Crystallized by Flash Lamp Annealing

Flash lamp annealing (FLA) is a method of quickly crystallizing large areas of amorphous silicon, which is a promising alternative to existing low-throughput laser annealing in the fabrication of low temperature polycrystalline silicon for thin film transistors in display applications [1]. However, FLA tends to promote dewet- ting of silicon and randomized void formation during melt-phase crystallization [2]. Chromium underlayers have been successfully used [3] to promote silicon adhesion in thicker films, but there are many potential interactions between Cr and Si, such as the formation of silicides and generation of electrical trap states, that may inhibit future transistor performance. The mechanism and effects of these interactions are not yet understood. This work investigates the efficacy of chromium adhesion layers in silicon crystallization by FLA. Various thicknesses and configurations of amorphous silicon, thin chromium, and silicon dioxide barriers were deposited on glass and subjected to FLA. The resulting material was analyzed with electron and atomic-probe microscopy and found to contain a unique repeated pattern of voids, trenches, and SEM-bright spots at the nanometer scale. Energy-dispersive X-ray spectroscopy confirmed the distribution of chromium in crystallized films to be discrete Cr-rich agglomerations 50-70 nm in diameter, with little metallic contamination outside of these isolated areas

Recent Advances in Thin Film Electronic Devices

This reprint is a collection of the papers from the Special Issue “Recent Advances in Thin Film Electronic Devices” in Micromachines. In this reprrint, 1 editorial and 11 original papers about recent advances in the research and development of thin film electronic devices are included. Specifically, three research fields are covered: device fundamentals (5 papers), fabrication processes (5 papers), and testing methods (1 paper). The experimental data, simulation results, and theoretical analysis presented in this reprint should benefit those researchers in flat panel displays, flat panel sensors, energy devices, memories, and so on

Investigations on thin film polysilicon MOSFETs with Si-Ge ion implanted channels

Thin Film Transistors have been fabricated in 0.2 urn thick polycrystalline silicon. NMOS and PMOS devices were fabricated on four groups of substrates. One group was processed with as deposited polysilicon and three of the substrates received high dose implants of Si and/or Ge prior to anneal. The Si implants were designed to amorphize the film by a process known as Seed Selection through Ion Channeling (SSIC), and the Ge was implanted just below the surface to enhance transistor characteristics. Two of the groups, one which received Ge implanted just below the surface and the other no implant at all, did not show much of any improvements in either the NMOS or the PMOS devices. Wafers that received double Si implants prior to substrate anneal, allowed the NMOS devices to exhibit better transistor qualities than any of the other implants, while the PMOS devices exhibited very poor qualities. Substrates that received a high energy high dose Si implant and Ge implanted just below the surface at a high dose to create a Si-Ge channel, demonstrated a 100% increase in hole mobility on 2 urn channel length devices over the double Si implanted substrates. The drain current of the Si-Ge PMOS devices was -260 uA as compared to -16 uA for the double Si implanted substrates for VGS=-7 V at VDS=3.0 V. The subthreshold swing was much larger at 2.1 V/dec for the Si- Ge channel PMOS devices as compared to and average of about 0.5 V/dec for all the other PMOS devices. The undesirable leakage observed in the subthreshold swing can be attributed to the grain structure of the Si-Ge layer in the channel. These effects can be minimized by further enhancement of grain sizes and passivation of the grain boundaries

Amorphous metal oxide semiconductor thin film transistors for printed electronics

There is an acute market need for solution-processable semiconductor inks that can form the essential components of the printed analog and digital circuits. Currently, the industry is migrating beyond simply printing conductive metals for interconnects and embracing higher integration by printing transistors directly on the same substrate. This thesis focuses on investigating solution-processed amorphous indium gallium zinc oxide (IGZO) as a semiconducting channel layer of a field-effect transistor to enable low-cost, large-area printed electronics that are physically flexible and optically transparent. Specifically, we aim to achieve field-effect mobility exceeding 1 cm2/Vs, to overcome the limits faced in existing amorphous silicon and emerging organic transistor technologies, through optimizing IGZO ink and studying various thin-film processing conditions. Device approach using solution-processed, high-K aluminum oxide dielectric layer has also been examined in this study. In addition, the effect of low-temperature UV-assisted annealing has been studied which allow the fabrication to be compatible with plastic substrates

\u3cem\u3eMaterials Integration and Device Fabrication of Active Matrix Thin Film Transistor Arrays for Intracellular Gene Delivery\u3c/em\u3e

Materials and process integration of a thin film transistor array for intra/extracellular probing are described in this study. A combinatorial rf magnetron sputter deposition technique was employed to investigate the electrical characteristics and micro-structural properties of molybdenum tungsten (MoW) high temperature electrodes as a function of the binary composition. In addition to the composition, the effect of substrate bias and temperature was investigated. The electrical resistivity of MoW samples deposited at room temperature with zero bias followed the typical Nordheim’s rule as a function of composition. The resistivity of samples deposited with substrate bias is uniformly lower and obeyed the rule of mixtures as a function of composition. The metastable β-W phase was not observed in the biased films even when deposited at room temperature. High resolution scanning electron microscopy revealed a more dense structure for the biased films, which correlated to the significantly lower film resistivity. In order to overcome deficiencies in sputtered silicon dioxide (SiO2) films the rf magnetron sputtering process was optimized by using a full factorial design of experiment (DOE). The optimized SiO2 film has a 5.7 MV/cm breakdown field and a 6.2 nm/min deposition rate at 10 W/cm2 RF power, 3 mTorr pressure, 300 °C substrate temperature, and 56 V substrate bias. Thin film transistors (TFTs) were also fabricated and characterized to show the prospective applications of the optimized SiO2 films. The effect that direct current (DC) substrate bias has on radio frequency (RF)-sputter-deposited amorphous silicon (a-Si) films was also investigated. The substrate bias produces a denser a-Si film with fewer defects compared to unbiased films. The reduced number of defects results in a higher resistivity because defect-mediated conduction paths are reduced. Thin film transistors (TFT) that were completely sputter-deposited were fabricated and characterized. The TFT with the biased a-Si film showed lower leakage (off-state) current, higher on/off current ratio, and higher transconductance (field effect mobility) than the TFT with the unbiased a-Si film. The crystallization properties of amorphous silicon (a-Si) thin film deposited by rf magnetron sputter deposition with substrate bias have been thoroughly characterized. The crystallization speed can be increased and the crystallization temperature can be drastically lowered relative to unbiased a-Si even though the stress state of biased a-Si film is highly compressive. The substrate bias enhances defect formation (vacancies, dislocations, stacking faults) via ion bombardment during the film growth, which effectively increases the driving force for crystallization of the films. The electrical and optical properties of sputter-deposited silicon nitride (SiNx) and n+ amorphous silicon (n+ a-Si) films as a function of substrate bias during sputter deposition were investigated. The breakdown voltage of sputter-deposited SiNx with 20 W (125 V) substrate bias is 7.65 MV/cm which is equivalent to that of plasma enhanced chemical vapor deposition (PECVD) SiNx films. The conductivity of n+ a-Si films are also enhanced by applying substrate bias during the sputter deposition. To verify the effect of substrate bias, amorphous silicon thin film transistors (TFTs) were fabricated with substrate biased thin films and compared their electrical properties with conventional sputter deposited TFTs. Lastly, electrochemical measurements were analyzed using gold and pyrrole solution to verify the active addressability of the TFT array fabricated by entirely by sputter deposited thin films below 200 °C temperature