Energy-Aware Scheduling for Streaming Applications

Streaming applications have become increasingly important and widespread,with application domains ranging from embedded devices to server systems.Traditionally, researchers have been focusing on improving the performanceof streaming applications to achieve high throughput and low response time.However, increasingly more attention is being shifted topower/performance trade-offbecause power consumption has become a limiting factor on system designas integrated circuits enter the realm of nanometer technology.This work addresses the problem of scheduling a streaming application(represented by a task graph)with the goal of minimizing its energy consumptionwhile satisfying its two quality of service (QoS) requirements,namely, throughput and response time.The available power management mechanisms are dynamic voltage scaling (DVS),which has been shown to be effective in reducing dynamic power consumption, andvary-on/vary-off, which turns processors on and off to save static power consumption.Scheduling algorithms are proposed for different computing platforms (uniprocessor and multiprocessor systems),different characteristics of workload (deterministic and stochastic workload),and different types of task graphs (singleton and general task graphs).Both continuous and discrete processor power models are considered.The highlights are a unified approach for obtaining optimal (or provably close to optimal)uniprocessor DVS schemes for various DVS strategies anda novel multiprocessor scheduling algorithm that exploits the differencebetween the two QoS requirements to perform processor allocation,task mapping, and task speedscheduling simultaneously

Memory-Aware Scheduling for Fixed Priority Hard Real-Time Computing Systems

As a major component of a computing system, memory has been a key performance and power consumption bottleneck in computer system design. While processor speeds have been kept rising dramatically, the overall computing performance improvement of the entire system is limited by how fast the memory can feed instructions/data to processing units (i.e. so-called memory wall problem). The increasing transistor density and surging access demands from a rapidly growing number of processing cores also significantly elevated the power consumption of the memory system. In addition, the interference of memory access from different applications and processing cores significantly degrade the computation predictability, which is essential to ensure timing specifications in real-time system design. The recent IC technologies (such as 3D-IC technology) and emerging data-intensive real-time applications (such as Virtual Reality/Augmented Reality, Artificial Intelligence, Internet of Things) further amplify these challenges. We believe that it is not simply desirable but necessary to adopt a joint CPU/Memory resource management framework to deal with these grave challenges. In this dissertation, we focus on studying how to schedule fixed-priority hard real-time tasks with memory impacts taken into considerations. We target on the fixed-priority real-time scheduling scheme since this is one of the most commonly used strategies for practical real-time applications. Specifically, we first develop an approach that takes into consideration not only the execution time variations with cache allocations but also the task period relationship, showing a significant improvement in the feasibility of the system. We further study the problem of how to guarantee timing constraints for hard real-time systems under CPU and memory thermal constraints. We first study the problem under an architecture model with a single core and its main memory individually packaged. We develop a thermal model that can capture the thermal interaction between the processor and memory, and incorporate the periodic resource sever model into our scheduling framework to guarantee both the timing and thermal constraints. We further extend our research to the multi-core architectures with processing cores and memory devices integrated into a single 3D platform. To our best knowledge, this is the first research that can guarantee hard deadline constraints for real-time tasks under temperature constraints for both processing cores and memory devices. Extensive simulation results demonstrate that our proposed scheduling can improve significantly the feasibility of hard real-time systems under thermal constraints

Tolerisanje grešaka i energetska efikasnost kod sistema za rad u realnom vremenu sa vremenskom redundansom

The concept of real-time systems (RTSs) is presented in the computer science for decades. During that period, the RTSs have evolved from special purpose microcomputer systems for industrial application to various forms of embedded system that are deeply ingrained in wide segments of daily life. The new application domains pose new design requirements and goals to RTSs, which are now often required to provide both fault tolerance and energy efficiency in addition to their main objective to compute and deliver correct results within a specified period of time. There is a fundamental tradeoff between these two additional requirements because fault tolerance techniques use slack time to improve reliability while low energy consumption techniques exploits slack time to increase energy efficiency. The central problem considered in the dissertation is how to optimally distribute the slack time between these techniques. Dynamic voltage scaling (DVS) is known as one of the most effective low-energy technique for RTSs. However, most existing DVS techniques only focus on minimizing energy consumption without taking the fault-tolerant capability of RTSs into account. In order to solve specify problem in this dissertation, a new heuristic-based fault-tolerant dynamic voltage and frequency scaling (FT-DVFS) algorithm is developed. The goal of the proposed algorithm is to minimize the amount of energy consumed by a real-time system under fault tolerance constraints while guaranteeing that all real-time tasks can complete successfully before their deadlines. Basically, the FT-DVFS is a DVS algorithm with integrated response time analysis (RTA) to check both the schedulability and the fault tolerant constraints of real-time task sets. The performances of FT-DVFS algorithm are evaluated by simulation in a custom build simulator. The simulation results are analyzed from three different points of view: the schedulability, the energy consumption, and the fault tolerance. The simulation results show that the proposed algorithm saves a significant amount of energy even with only two frequency/voltage levels, and the savings further increases with the increase of the number of frequency levels. Also, the simulations show that the reduction in power consumption, which can be achieved with FT-DVFS algorithm decreases with the increase of the processor utilization factor (i.e. processor spare time). The simulation results from the fault tolerant point of view show that the higher level of fault tolerance can only be attained through sacrificing a part of savings in power consumption, and vice versa. The proposed heuristic FT-DVFS algorithm is compared with the optimal DVS algorithm. The simulation analysis show that FT-DVFS algorithm achieves near-optimal solutions in very short computation time even for large task sets

User experience driven CPU frequency scaling on mobile devices towards better energy efficiency

With the development of modern smartphones, mobile devices have become ubiquitous in our daily lives. With high processing capabilities and a vast number of applications, users now need them for both business and personal tasks. Unfortunately, battery technology did not scale with the same speed as computational power. Hence, modern smartphone batteries often last for less than a day before they need to be recharged. One of the most power hungry components is the central processing unit (CPU). Multiple techniques are applied to reduce CPU energy consumption. Among them is dynamic voltage and frequency scaling (DVFS). This technique reduces energy consumption by dynamically changing CPU supply voltage depending on the currently running workload. Reducing voltage, however, also makes it necessary to reduce the clock frequency, which can have a significant impact on task performance. Current DVFS algorithms deliver a good user experience, however, as experiments conducted later in this thesis will show, they do not deliver an optimal energy efficiency for an interactive mobile workload. This thesis presents methods and tools to determine where energy can be saved during mobile workload execution when using DVFS. Furthermore, an improved DVFS technique is developed that achieves a higher energy efficiency than the current standard. One important question when developing a DVFS technique is: How much can you slow down a task to save energy before the negative effect on performance becomes intolerable? The ultimate goal when optimising a mobile system is to provide a high quality of experience (QOE) to the end user. In that context, task slowdowns become intolerable when they have a perceptible effect on QOE. Experiments conducted in this thesis answer this question by identifying workload periods in which performance changes are directly perceptible by the end user and periods where they are imperceptible, namely interaction lags and interaction idle periods. Interaction lags are the time it takes the system to process a user interaction and display a corresponding response. Idle periods are the periods between interactions where the user perceives the system as idle and ready for the next input. By knowing where those periods are and how they are affected by frequency changes, a more energy efficient DVFS governor can be developed. This thesis begins by introducing a methodology that measures the duration of interaction lags as perceived by the user. It uses them as an indicator to benchmark the quality of experience for a workload execution. A representative benchmark workload is generated comprising 190 minutes of interactions collected from real users. In conjunction with this QOE benchmark, a DVFS Oracle study is conducted. It is able to find a frequency profile for an interactive mobile workload which has the maximum energy savings achievable without a perceptible performance impact on the user. The developed Oracle performance profile achieves a QOE which is indistinguishable from always running on the fastest frequency while needing 45% less energy. Furthermore, this Oracle is used as a baseline to evaluate how well current mobile frequency governors are performing. It shows that none of these governors perform particularly well and up to 32% energy savings are possible. Equipped with a benchmark and an optimisation baseline, a user perception aware DVFS technique is developed in the second part of this thesis. Initially, a runtime heuristic is introduced which is able to detect interaction lags as the user would perceive them. Using this heuristic, a reinforcement learning driven governor is developed which is able to learn good frequency settings for interaction lag and idle periods based on sample observations. It consumes up to 22% less energy than current standard governors on mobile devices, and maintains a low impact on QOE