Effect Of Nanosecond Laser Dicing On Ultrathin Silicon Die With Copper Stabilization Layer

Die ultra-nipis memerlukan satu lapisan kuprum (Cu) penstabilan di belakangnya untuk menghalang ledingan dan retakan semasa proses pengimpalan die serta penyambungan dawai. Pemotongan wafer silikon (Si) dengan lapisan Cu di belakangnya sangat mencabar. Pemotongan dengan bilah secara mekanikal akan mengakibatkan tersumbatnya bilah tersebut dan kerosakan akan dialami. Hasilannya, kerosakan die akan berlaku. Pemotongan menggunakan plasma berkos tinggi dan memerlukan proses tambahan seperti fotolitografi dan punaran. Pemotongan dengan laser mempuntai prospek yang baik dan sekarang ianya digunakan untuk memotong wafer Si yang nipis. Tetapi, tiada kajian yang melaporkan penggunaan teknik ini untuk memotong wafer ultra-nipis dengan lapis Cu dibelakang. Kajian ini menunjukkan kebolehan untuk menghasilkan wafer Si ultra-nipis setebal 20 μm dengan lapisan Cu depan setebal 5-20 μm dan belakang setebal 10-30 μm. Ketebalan lapisan logam dan Si berada dalam 10% sasaran proses. Tiada pengasingan di antaramuka dapat dikesan. Keupayaan pemotongan atas wafer Si ultra-nipis dengan 10-30 μm lapisan Cu di belakang dengan menggunakan laser nano-saat ultra-ungu telah dibuktikan. Kesan laser nano-saat ke atas kekuatan dinding tepi die telah dinilai berasaskan ujian bengkok tiga titik (3PB). Ultrathin dies require a Cu stabilization layer, which is essentially a backside Cu layer, to prevent warpage and cracks during solder die attach and wire bonding. The dicing of Si wafers with a backside Cu layer is challenging. Mechanical blade dicing through the Cu layer causes blade clogging and damage, which eventually results in severe die chipping and cracks. Plasma dicing is costly as it requires additional photolithography and etching steps. Laser dicing is promising and is currently used to singulate thin Si wafers. However, there is no reported work on its application for dicing ultrathin wafers with a backside Cu layer. In this work, the feasibility of fabricating 20 μm ultrathin Si wafers with 5-20 μm frontside Cu and 10-30 μm backside Cu has been shown. The thicknesses of the metal and Si layers are within 10% of the process target. No interfacial delamination was detected. The feasibility of dicing through 20 μm ultrathin Si wafers with 10-30 μm backside Cu with nanosecond UV laser have also been demonstrated. The effect of nanosecond laser dicing on the die sidewall strength was evaluated with the three-point bend (3PB) test

Characterization of Flexible Hybrid Electronics Using Stretchable Silver Ink and Ultra-Thin Silicon Die

Flexible Hybrid Electronics (FHEs) offer many advantages to the future of wearable technology. By combining the dynamic performance of conductive inks, and the functionality of ultra-thinned, traditional IC technology, new FHE devices allow for development of applications previously excluded by relying on a specific type of electronics technology. The characterization and reliability analysis of stretchable conductive inks paired with ultra-thin silicon die in theµm range was conducted. A silver based ink designed to be stretchable was screen printed on a TPU substrate and cured using box oven, conveyor convection oven, and photonic curing processes. Reliability tests were conducted including a tape test, crease test, wash test, and abrasion test. Optimization of each curing process resulted in all three methods’ ability to achieve the ink sheet resistance specification of \u3c75mΩ/square/25µm. Reliability tests on the printing concluded that, if fully cured, all samples achieve similar reliability performance. Additionally, a series of 10 mm x 10 mm ultra-thin die were characterized using stylus profilometry and optical measurement in order to test the die quality and readiness for assembly. The die had been thinned from an initial thickness down of 600 µm to a target of 50 µm. A direct inverse relationship was shown between die thickness and die warpage, likely due to high levels of internal stress caused by the dicing and thinning process. Finally, an innovate pairing of serpentine copper clad traces on TPU was tested for reliability performance using traditional solder for die attachment

Vertically integrated modules for low power embedded sensor systems

A typical embedded sensor system consists of an environmental sensor, data storage, and a control circuit (such as a microcontroller). Two main traits desired of these embedded sensor systems are small form factor and low power consumption. However, due to the diverse nature of the design and applications, monolithic solutions incorporating the three main components are often not available on a large cost effective scale. This work describes a method of integrating heterogeneous circuit components into a single module. When combined with efficient operating algorithms the system size is reduced and lifetime is extended. Production or custom designed component chips are thinned and stacked vertically while interconnects are fabricated within the module providing a 3-D integration (3DI) of the system. A Global Positioning System (GPS) location recording sensor system is designed with the intention of applying the 3DI process to reduce its size and power consumption

Reliability analysis of foil substrate based integration of silicon chips

Flexible electronics has attracted significant attention in the recent past due to the booming wearables market in addition to the ever-increasing interest for faster, thinner and foldable mobile phones. Ultra-thin bare silicon ICs fabricated by thinning down standard ICs to thickness below 50 μm are flexible and therefore they can be integrated on or in polymer foils to create flexible hybrid electronic (FHE) components that could be used to replace rigid standard surface mount device (SMD) components. The fabricated FHE components referred as chip foil packages (CFPs) in this work are ideal candidates for FHE system integration owing to their ability to deliver high performance at low power consumption while being mechanically flexible. However, very limited information is available in the literature regarding the reliability of CFPs under static and dynamic bending. The lack of such vital information is a major obstacle impeding their commercialization. With the aim of addressing this issue, this thesis investigates the static and dynamic bending reliability of CFPs. In this scope, the static bending reliability of CFPs has been investigated in this thesis using flexural bending tests by measuring their fracture strength. Then, Finite Element Method (FEM) simulations have been implemented to calculate the fracture stress of ultra-thin flexible silicon chips where analytical formulas may not be applied. After calculating the fracture stress from FEM simulations, the enhancement in robustness of ultra-thin chips (UTCs) against external load has also been proved and quantified with further experimental investigations. Besides, FEM simulations have also been used to analyse the effect of Young’s Modulus of embedding materials on the robustness of the embedded UTCs. Furthermore, embedding the UTCs in polymer layers has also been experimentally proven to be an effective solution to reduce the influence of thinning and dicing induced damages on the robustness of the embedded UTCs. Traditional interconnection techniques such as wire bonding may not be implemented to interconnect ultra-thin silicon ICs owing to the high mechanical forces involved in the processes that would crack the chips. Therefore, two novel interconnection methods namely (i) flip-chip bonding with Anisotropic Conductive Adhesive (ACA) and (ii) face-up direct metal interconnection have been implemented in this thesis to interconnect ultra-thin silicon ICs to the corresponding interposer patterns on foil substrates. The CFP samples thus fabricated were then used for the dynamic bending reliability investigations. A custom-built test equipment was developed to facilitate the dynamic bending reliability investigations of CFPs. Experimental investigations revealed that the failure of CFPs under dynamic bending was caused mainly by the cracking of the redistribution layer (RDL) interconnecting the chip and the foil. Furthermore, it has also been shown that the CFPs are more vulnerable to repeated compressive bending than to repeated tensile bending. Then, the influence of dimensional factors such as the thickness of the chip as well as the RDL on the dynamic bending reliability of CFPs have also been studied. Upon identifying the plausible cause behind the cracking of the RDL leading to the failure of the CFPs, two methods to improve the dynamic bending reliability of the RDL have been suggested and demonstrated with experimental investigations. The experimental investigations presented in this thesis adds some essential information to the state-of-the-art concerning the static and the dynamic bending reliability of UTCs integrated in polymer foils that are not yet available in the literature and aids to establish in-depth knowledge of mechanical reliability of the components required for manufacturing future FHE systems. The strategies devised to enhance the robustness of UTCs and CFPs could serve as guidelines for fabricating reliable FHE components and systems

An Investigation of Micro and Nanoscale Molding for Biomedical Applications

In the last decade, there has been rapid advancement of micro and nano manufacturing. Microinjection molding is a cost-effective fabrication technique that can fulfill the requirements of many medical applications. Despite the many advancements of microi

Mechanical Properties and Fatigue of Polycrystalline Silicon under Static and High Frequency Cyclic Loading

10 and 20µm thick n-doped, epitaxially deposited, Bosch polysilicon layers of columnar structure were investigated. In order to characterize the fracture strength and fatigue,specimens with different sizes and geometries were designed and tested under static and high frequency cycling loading. Fractographic analysis has given an insight into fracture mechanism and helped to identify typical fracture modes and defects types

Micromachining

To present their work in the field of micromachining, researchers from distant parts of the world have joined their efforts and contributed their ideas according to their interest and engagement. Their articles will give you the opportunity to understand the concepts of micromachining of advanced materials. Surface texturing using pico- and femto-second laser micromachining is presented, as well as the silicon-based micromachining process for flexible electronics. You can learn about the CMOS compatible wet bulk micromachining process for MEMS applications and the physical process and plasma parameters in a radio frequency hybrid plasma system for thin-film production with ion assistance. Last but not least, study on the specific coefficient in the micromachining process and multiscale simulation of influence of surface defects on nanoindentation using quasi-continuum method provides us with an insight in modelling and the simulation of micromachining processes. The editors hope that this book will allow both professionals and readers not involved in the immediate field to understand and enjoy the topic