59 research outputs found
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Scaling and process effect on electromigration reliability for Cu/low k interconnects
textThe microelectronics industry has been managing the RC delay problem arising from aggressive line scaling, by replacing aluminum (Al) by copper (Cu) and oxide dielectric by low-k dielectric. Electromigration (EM) turned out to be a serious reliability problem for Cu interconnects due to the implementation of mechanically weaker low-k dielectrics. In addition, line width and via size scaling resulted in the need of a novel diffusion barrier, which should be uniform and thin. The objective of this dissertation is to investigate the impacts of Ta barrier process, such as barrier-first and pre-clean first, and scaling of barrier and line/via on EM reliability of Cu/low-k interconnects. For this purpose, EM statistical test structures, having different number of line segments, line width, and via width, were designed. The EM test structures were fabricated by a dualdamascene process with two metal layers (M1/Via/M2), which were then packaged for EM tests. The package-level EM tests were performed in a specially designed vacuum chamber with pure nitrogen environment. The novel barrier deposition process, called barrier-first, showed a higher (jL)[subscript c] product and prolonged EM lifetime, compared with the conventional Ta barrier deposition process, known as pre-clean first. This can be attributed to the improved uniformity and thickness of the Ta layer on the via and trench, as confirmed by TEM. As for the barrier thickness effect, the (jL)c product decreased with decreasing thickness, due to reduced Cu confinement. A direct correlation between via size and EM reliability was found; namely, EM lifetime and statistics degraded with via size. This can be attributed to the fact that critical void length to cause open circuit is about the size of via width. To investigate further line scaling effect on EM reliability, SiON (siliconoxynitride) trenchfilling process was introduced to fabricate 60-nm lines, corresponding to 45-nm technology, using a conventional, wider line lithograph technology. The EM lifetime of 60-nm fine lines with SiON filling was longer than that of a standard damascene structure, which can be attributed to a distinct via/metal-1 configuration in reducing process-induced defects at the via/metal-1 interface.Materials Science and Engineerin
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Study of initial void formation and electron wind force for scaling effects on electromigration in Cu interconnects
textThe continuing scaling of integrated circuits beyond 22nm technology node poses increasing challenges to Electromigration (EM) reliability for Cu on-chip interconnects. First, the width of Cu lines in advanced technology nodes is less than the electron mean free path which is 39nm in Cu at room temperature. This is a new size regime where any new scaling effect on EM is of basic interest. And second, the reduced line width necessitates the development of new methods to analyze the EM characteristics. Such studies will require the development of well controlled processes to fabricate suitable test structures for EM study and model verification. This dissertation is to address these critical issues for EM in Cu interconnects. The dissertation first studies the initial void growth under EM, which is critical for measurement of the EM lifetime and statistics. A method based on analyzing the resistance traces obtained from EM tests of multi-link structures has been developed. The results indicated that there are three stages in the resistance traces where the rate of the initial void growth in Stage I is lower than that in Stage III after interconnect failure and they are linearly correlated. An analysis extending the Korhonen model has been formulated to account for the initial void formation. In this analysis, the stress evolution in the line during void growth under EM was analyzed in two regions and an analytic solution was deduced for the void growth rate. A Monte Carlo grain growth simulation based on the Potts model was performed to obtain grain structures for void growth analysis. The results from this analysis agreed reasonably well with the EM experiments. The next part of the dissertation is to study the size effect on the electron wind force for a thin film and for a line with a rectangular cross section. The electron wind force was modeled by considering the momentum transfer during collision between electrons and an atom. The scaling effect on the electron wind force was found to be represented by a size factor depending on the film/line dimensions. In general, the electron wind force is enhanced with increasing dimensional confinement. Finally, a process for fabrication of Si nanotrenches was developed for deposition of Cu nanolines with well-defined profiles. A self-aligned sub-lithographic mask technique was developed using polymer residues formed on Si surfaces during reactive ion etching of Si dioxide in a fluorocarbon plasma. This method was capable to fabricate ultra-narrow Si nanotrenches down to 20nm range with rectangular profiles and smooth sidewalls, which are ideal for studying EM damage mechanisms and model verification for future technology nodes.Physic
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Effects of scaling and grain structure on electromigration reliability of Cu interconnects
textElectromigration (EM) remains a major reliability concern for on-chip Cu interconnects due to the continuing scaling and the introduction of new materials and processes. In Cu interconnects, the atomic diffusion along the Cu/SiCN cap interface dominates the mass transport and thus controls EM reliability. The EM lifetime degrades by half for each new generation due to the scaling of the critical void volume which induces the EM failure. To improve the EM performance, a metal cap such as CoWP was applied to the Cu surface to suppress the interfacial diffusion. By this approach, two orders of magnitude improvement in the EM lifetime was demonstrated. For Cu lines narrower than 90 nm, the Cu grain structure degraded from bamboo-like grains to polycrystalline grains due to the insufficient grain growth in the trench. Such a change in Cu grain structures can increase the mass transport through grain boundaries and thus degrade the EM performance. The objective of this study is to investigate the scaling effect on EM lifetime and Cu microstructure, and more importantly, the grain structure effect on EM behaviors of Cu interconnects with the CoWP cap compared to those with the SiCN cap only.
This thesis is organized into three parts. In the first part, the effect of via scaling on EM reliability was studied by examining two types of specially designed test structures. The EM lifetime degraded with the via size scaling because the critical void size that causes the EM failure is the same with the via size. The line scaling effect on Cu grain structures were identified by examining Cu lines down to 60 nm in width using both plan-view and cross-sectional view transmission electron microscopy.
In the second part, the effect of grain structure was investigated by examining the EM lifetime, statistics and failure modes for Cu interconnects with different caps. A more significant effect of the grain structure on EM characteristics was observed for the CoWP cap compared to the SiCN cap. For the CoWP cap, the grain structure not only affected the mass transport rate along the Cu line, but also impacted the flux divergence site distribution which determined the voiding location and the lifetime statistics.
Finally, the effect of grain structure on EM characteristics of CoWP capped Cu interconnects was examined using a microstructure-based statistical model. In this model, the microstructure of Cu interconnects was simplified as cluster and bamboo grains connected in series. Based on the weakest-link approximation, it was shown that the EM lifetime and statistics could be adequately modeled by combining the measured cluster length distribution with the EM lifetime-cluster length correlation for each individual failure unit.Electrical and Computer Engineerin
Study of Tantalum nitride diffusion barrier films for coppper interconnect technology
As technology progressed to ultra - large scale integration leading to smaller and smaller devices, there are continuous challenges in the fields of materials, processes and circuit designs. Copper is the interconnect material of choice because of its low electrical resistivity and high electromigration resistance. However, copper is quite mobile in silicon at elevated temperatures. Therefore, to prevent the diffusion of copper into silicon, a diffusion barrier layer that has fewer grain boundaries, good adhesion to Si and Si02, high thermal and electrical stability with respect to Cu is necessary. Tantalum nitride compounds have been investigated as potential barrier materials. TaN has a very high melting point of 2950C. It is thermodynamically stable with respect to Cu and has good adhesion to the substrate. It has a dense microstructure and shows good resistance to heavy mobility of Cu in Si and has electrical stability at temperatures upto 750 C. The diffusion barrier properties of Ta and its nitrides for copper metallization at RIT have been investigated. The TaNx films were reactively sputter deposited on Si02 substrates at various N2/AJ- ratios. The influence of nitrogen partial pressure on the electrical and structural properties of the films is studied. It has been observed that as deposited pure Ta is tetragonal, which becomes bcc-Ta with small increase in N2 flow to 5% of the sputtering gas mixture. When the nitrogen flow is increased from 12 up to 20%, amorphous and a mixture of amorphous and crystalline Ta2N phase is formed. The amorphous phase crystallizes when annealed to higher temperatures. An fee- TaN phase is formed at N2 flow of 30%. At higher concentrations of N2; nitrogen rich compounds like Ta5N6, Ta3N5 are formed. During backend semiconductor processing, both Cu and TaN films are subjected to various annealing treatments in N2, 02, and Ar at relatively high temperatures. Since these treatments influence the stability of the metallization it was important to establish the effect of the ambients on the integrity of the copper interconnect. The Cu/TaN/Si02 films were annealed to various temperatures up to 600 C in N2, Ar ambients for 20 min and the thermal stability and barrier effectiveness of the films was studied. Annealing the films to temperatures above 500 C cause de-lamination of films at the Cu/TaN interface, which is attributed to the formation of copper oxides with a high density of voids. This was observed by XRD analyis and SEM. RBS spectra showed diffusion of tantalum into the surface of copper at temperatures ~ 500 to 600 C. Therefore we can conclude that cubic TaN films act as stable barrier films up to 500 C in an inert ambient
Effects of sputter deposition parameters on stress in tantalum films with applications to chemical mechanical planarization of copper
Attempts to introduce a CMP process for copper damascene features at Rochester Institute of Technology were stymied by adhesion failures of the Ta/Cu film stack. This work was undertaken to investigate the effect of stress in the films on adhesion and to develop a viable CMP process for Cu damascene technology. In depth studies of stress as a function of sputter deposition conditions revealed that stress in Ta layers could vary from -1700 MPa compression to +800 MPa tensile for deposition pressures over a range of 2-20 mTorr for films having a nominal thickness of 0.25 μm. For a fixed pressure, stress could vary from -1500 to +800 MPa for thicknesses ranging from 24 to 225 nm. More importantly, target aging was shown to result in a change in stress for fixed deposition parameters, such as pressure and power. Control of the stress in these films is critical as a substantial difference in CMP removal rates for tantalum films having -400 to -1200 MPa of compressive stress was observed. In addition, the top copper layer will adhere to Ta films in a specific range of compressive stress. A 50 nm film stack of TaN/Ta with varying thickness ratios of the two metals was fabricated that exhibited nearly constant compressive stress. This deposition process for the TaN/Ta barrier layer was developed utilizing fixed voltage, not power as the deposition parameter. These studies resulted in a sputter process for TaN/Ta/Cu that exhibited good adhesion to SiO2, both for blanket and patterned films. A copper damascene process has been developed using a film system that adhered well to SiO2. Wafers were characterized for planarity both within die and within wafer, as well as wafer-to-wafer. The most promising deposition and polish processes were employed to produce a metal gate metal oxide semiconductor (MOS) capacitor and characterized by measuring the maximum electric field of the gate oxide before it would break down. The planarized damascene features were achieved that exhibited ≤ 30 nm of topology as viewed by profilometery and AFM. Results of breakdown studies of MOS capacitors were confounded by particulate effects, but the capacitors produced by CMP were on par with sputtered films patterned by photolithography. I would like to express my gratitude to Dr. Michael Jackson for taking me on as his graduate student and for his guidance throughout this project. I am grateful for Dr. Santosh Kurinec, Dr. Richard Lane and Dr. Christopher Hoople for being on my thesis committee and being willing to donate time to answer my questions. I acknowledge Dr. Tom Blanton for his generous donation of XRD analysis and expertise. I also appreciate the help of Daniel Brown for writing a program to perform stress calculations. This endeavor saved a significant amount of time. I give my most sincere appreciation to my father for providing help in numerous ways
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Electromigration modeling and layout optimization for advanced VLSI
textElectromigration (EM) is a critical problem for interconnect reliability in advanced VLSI design. Because EM is a strong function of current density, a smaller cross-sectional area of interconnects can degrade the EM-related lifetime of IC, which is expected to become more severe in future technology nodes. Moreover, as EM is governed by various factors such as temperature, material property, geometrical shape, and mechanical stress, different interconnect structures can have distinct EM issues and solutions to mitigate them. For example, one of the most prominent technologies, die stacking technology of three-dimensional (3D) ICs, can have different EM problems from that of planer ICs, due to their unique interconnects such as through-silicon vias (TSVs).
This dissertation investigates EM in various interconnect structures, and applies the EM models to optimize IC layout. First, modeling of EM is developed for chip-level interconnects, such as wires, local vias, TSVs, and multi-scale vias (MSVs). Based on the models, fast and accurate EM-prediction methods are proposed for the chip-level designs. After that, by utilizing the EM-prediction methods, the layout optimization methods are suggested, such as EM-aware routing for 3D ICs and EM-aware redundant via insertion for the future technology nodes in VLSI.
Experimental results show that the proposed EM modeling approaches enable fast and accurate EM evaluation for chip design, and the EM-aware layout optimization methods improve EM-robustness of advanced VLSI designs.Electrical and Computer Engineerin
Estudo da eletromigração em circuitos integrados na fase de projeto
Orientadores: Roberto Lacerda de Orio, Leandro Tiago ManeraTese (doutorado) - Universidade Estadual de Campinas, Faculdade de Engenharia Elétrica e de ComputaçãoResumo: O dano por eletromigração nas interconexões é um gargalo bem conhecido dos circuitos integrados, pois causam problemas de confiabilidade. A operação em temperaturas e densidades de corrente elevadas acelera os danos, aumentando a resistência da interconexão e, portanto, reduzindo a vida útil do circuito. Este problema tem se acentuado com o escalonamento da tecnologia. Para garantir a confiabilidade da interconexão e, como consequência, a confiabilidade do circuito integrado, métodos tradicionais baseados no chamado Efeito Blech e numa densidade de corrente máxima permitida são implementados durante o projeto da interconexão. Esses métodos, no entanto, não levam em consideração o impacto da eletromigração no desempenho do circuito. Neste trabalho, a abordagem tradicional é estendida e um método para avaliar o efeito da eletromigração no desempenho de circuito integrado é desenvolvido. O método é implementado em uma ferramenta que identifica as interconexões críticas em um circuito integrado e sugere larguras adequadas com base em diferentes critérios para mitigar os danos à eletromigração e aumentar a confiabilidade. Além disso, é determinada a variação dos parâmetros de desempenho do circuito conforme a resistência das interconexões aumenta. A ferramenta é incorporada ao fluxo de projeto do circuito integrado e usa os dados dos kits de projeto e relatórios diretamente disponíveis no ambiente de projeto. Uma análise precisa da distribuição de temperatura na estrutura de interconexão é essencial para uma melhor avaliação da confiabilidade da interconexão. Portanto, é implementado um modelo para calcular a temperatura em cada nível de metalização da estrutura de interconexão. A distribuição de temperatura nas camadas de metalização de diferentes tecnologias é investigada. É mostrado que a temperatura no Metal 1 da tecnologia Intel 10 nm aumenta 75 K, 12 K mais alta que no Metal 2. Como esperado, as camadas mais próximas dos transistores sofrem um aumento de temperatura mais significativo. A ferramenta é aplicada para avaliar eletromigração nas interconexões e na robustez de diferentes circuitos, como um oscilador em anel, um circuito gerador de tensão de referência tipo bandgap e um amplificador operacional. O amplificador operacional, em particular, é cuidadosamente estudado. A metodologia proposta identifica interconexões críticas que quando danificadas por eletromigração causam grandes variações no desempenho do circuito. No pior cenário, a frequência de corte do circuito varia 65% em 5 anos de operação. Uma descoberta interessante é que a metodologia proposta identifica interconexões críticas que não seriam identificadas pelos critérios tradicionais. Essas interconexões operam com densidades de corrente abaixo do limite recomendado pelas regras de projeto. No entanto, uma dessas interconexões leva a uma variação de 30% no ganho do amplificador operacional. Em resumo, a ferramenta proposta verificou que dos 20% de caminhos com uma densidade crítica de corrente, apenas 3% degradam significativamente o desempenho do circuito. Este trabalho traz o estudo da confiabilidade das interconexões e de circuitos integrados para a fase de projeto, o que permite avaliar a degradação do desempenho do circuito antecipadamente durante o seu desenvolvimento. A ferramenta desenvolvida permite ao projetista identificar interconexões críticas que não seriam detectadas usando o critério de densidade máxima de corrente, levando a uma análise mais ampla e precisa da robustez de circuitos integradosAbstract: Electromigration damage in interconnects is a well-known bottleneck of integrated circuits, because it causes reliability problems. Operation at high temperatures and current densities accelerates the damage, increasing the interconnect resistance and, therefore, reducing the circuit lifetime. This issue has been accentuated with the technology downscaling. To guarantee the interconnect reliability and, as a consequence, the integrated circuit reliability, traditional methods based on the so-called Blech Effect and on the maximum allowed current density are implemented during interconnect design. These methods, however, do not take into account the impact of the electromigration on the circuit performance. In this work the traditional approach is extended and a method to evaluate the effect of the electromigration in an integrated circuit performance is developed. The method is implemented in a tool which identifies the critical interconnect lines of an integrated circuit and suggests the proper interconnect width based on different criteria to mitigate the electromigration damage and to increase the reliability. In addition, the variation of performance parameters of the circuit as an interconnect resistance changes is determined. The tool is incorporated into the design flow of the integrated circuit and uses the data from design kits and reports directly available from the design environment. An accurate analysis of the temperature distribution on the interconnect structure is essential to a better assessment of the interconnect reliability. Therefore, a model to compute the temperature on each metallization level of the interconnect structure is implemented. The temperature distribution on the metallization layers of different technologies is investigated. It is shown that the temperature in the Metal 1 of the Intel 10 nm can increase by 75 K, 12 K higher than in the Metal 2. As expected, the layers that are closer to the transistors undergo a more significant temperature increase. The tool is applied to evaluate the interconnects and the robustness of different circuits, namely a ring oscillator, a bandgap voltage reference circuit, and an operational amplifier, against electromigration. The operational amplifier, in particular, is thoroughly studied. The proposed methodology identifies critical interconnects which under electromigration cause large variations in the performance of the circuit. In a worst-case scenario, the cutoff frequency of the circuit varies by 65% in 5 years of operation. An interesting finding is that the proposed methodology identifies critical interconnects which would not be identified by the traditional criteria. These interconnects have current densities below the limit recommended by the design rules. Nevertheless, one of such an interconnect leads to a variation of 30% in the gain of the operational amplifier. In summary, the proposed tool verified that from the 20% paths with a critical current density, only 3% degrades significantly the circuit performance. This work brings the study of the reliability of the interconnects and of integrated circuits to the design phase, which provides the assessment of a circuit performance degradation at an early stage of development. The developed tool allows the designer to identify critical interconnects which would not be detected using the maximum current density criterion, leading to more accurate analysis of the robustness of integrated circuitsDoutoradoEletrônica, Microeletrônica e OptoeletrônicaDoutor em Engenharia Elétrica88882.329437/2019-01CAPE
Intra-level dielectric reliability in deep sub-micron copper interconnects
Master'sMASTER OF ENGINEERIN
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