Random dopant-induced variability in Si-InAs nanowire tunnel FETs: a quantum transport simulation study

In this letter, we report a quantum transport simu- lation study of the impact of Random Discrete Dopants (RDD)s on Si-InAs nanowire p-type Tunnel FETs. The band-to-band tunneling is simulated using the non-equilibrium Green’s func- tion formalism in effective mass approximation, implementing a two-band model of the imaginary dispersion. We have found that RDDs induce strong variability not only in the OFF-state but also in the ON-state current of the TFETs. Contrary to the nearly normal distribution of the RDD induced ON-current variations in conventional CMOS transistors, the TFET’s ON- currents variations are described by a logarithmic distribution. The distributions of other Figures of Merit (FoM) such as threshold voltage and subthreshold swing are also reported. The variability in the FoM is analysed by studying the correlation between the number and the position of the dopants

A review of selected topics in physics based modeling for tunnel field-effect transistors

The research field on tunnel-FETs (TFETs) has been rapidly developing in the last ten years, driven by the quest for a new electronic switch operating at a supply voltage well below 1 V and thus delivering substantial improvements in the energy efficiency of integrated circuits. This paper reviews several aspects related to physics based modeling in TFETs, and shows how the description of these transistors implies a remarkable innovation and poses new challenges compared to conventional MOSFETs. A hierarchy of numerical models exist for TFETs covering a wide range of predictive capabilities and computational complexities. We start by reviewing seminal contributions on direct and indirect band-to-band tunneling (BTBT) modeling in semiconductors, from which most TCAD models have been actually derived. Then we move to the features and limitations of TCAD models themselves and to the discussion of what we define non-self-consistent quantum models, where BTBT is computed with rigorous quantum-mechanical models starting from frozen potential profiles and closed-boundary Schr\uf6dinger equation problems. We will then address models that solve the open-boundary Schr\uf6dinger equation problem, based either on the non-equilibrium Green's function NEGF or on the quantum-transmitting-boundary formalism, and show how the computational burden of these models may vary in a wide range depending on the Hamiltonian employed in the calculations. A specific section is devoted to TFETs based on 2D crystals and van der Waals hetero-structures. The main goal of this paper is to provide the reader with an introduction to the most important physics based models for TFETs, and with a possible guidance to the wide and rapidly developing literature in this exciting research field

Vertical III-V Nanowire Transistors for Low-Power Electronics

Power dissipation has been the major challenge in the downscaling of transistor technology. Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) have struggled to keep a low power consumption while still maintaining a high performance due to the low carrier mobilities of Si but also due to their inherent minimum inverse subthreshold slope (S ≥ 60 mV/dec) which is limited by thermionic emission. This thesis work studied the capabilities and limitations of III-V based vertical nanowire n-type Tunneling Field-Effect Transistor (TFET) and p-type MOSFET (PMOS). InAs/InGaAsSb/GaSb heterojunction was employed in the whole study. The main focus was to understand the influence of the device fabrication processes and the structural factors of the nanowires such as band alignment, composition and doping on the electrical performance of the TFET. Optimizations of the device processes including spacer technology improvement, Equivalent Oxide Thickness (EOT) downscaling, and gate underlap/overlap were explored utilizing structural characterizations. Systematic fine tuning of the band alignment of the tunnel junction resultedin achieving the best performing sub-40 mV/dec TFETs with S = 32 mV/decand ION = 4μA/μm for IOFF = 1 nA/μm at VDS = 0.3 V. The suitability of employing TFET for electronic applications at cryogenic temperatures has been explored utilizing experimental device data. The impact of the choice of heterostructure and dopant incorporation were investigated to identify the optimum operating temperature and voltage in different temperature regimes. A novel gate last process self-aligning the gate and drain contacts to the intrinsic and doped segments, respectively was developed for vertical InGaAsSb-GaAsSb core-shell nanowire transistors leading to the first sub-100 mV/dec PMOS with S = 75 mV/dec, significant ION/ IOFF = 104 and IMIN < 1 nA/μm at VDS = -0.5 V

Tunnel Field Effect Transistors Based on Two-Dimensional Material Van-der-Waals Heterostructures

The successful isolation of graphene in 2004 has attracted great interest to search for potential applications of this unique material and other newborn members of the two-dimensional (2-D) family in electronics, optoelectronics, spintronics and other fields. Compared to graphene, the 2-D transition metal dichalcogenides (TMDs) have the advantage of being semiconductors, which would allow their use for logic devices. In the past decade, significant developments have been made in this area, where opportunities and challenges co-exist. Stacking different 2-D materials significantly increases the already considerable design space, especially when a type-II band alignment is obtained. This chapter will describe the recent progresses in the tunnel field-effect transistors based on 2-D TMD van-der-Waals heterostructure, which is one of the promising candidates for increasingly important low-power mobile computation applications. Due to their small size, such devices are intrinsically dominated by quantum effects. This requires the adoption of a fairly general theory of transport, such as the nonequilibrium Green\u27s functions (NEGF) formalism, which is a method having been more-and-more used for the simulation of electron transport in nanostructures in recent years

Numerical simulation of advanced CMOS and beyond CMOS devices

Co-supervisore: Marco PalaopenLo scaling dei dispositivi elettronici e l'introduzione di nuove opzioni tecnologiche per l'aumento delle prestazioni richiede un costante supporto dal punto di vista della simulazione numerica. Questa tesi si inquadra in tale ambito ed in particolare si prefigge lo scopo di sviluppare due tool software completi basati su tecniche avanzate al fine di predire le prestazioni di dipositivi nano-elettronici progettati per i futuri nodi tecnologiciDottorato di ricerca in Ingegneria industriale e dell'informazioneembargoed_20131103Conzatti, Francesc

III-V compound semiconductor transistors—from planar to nanowire structures

Conventional silicon transistor scaling is fast approaching its limits. An extension of the logic device roadmap to further improve future performance increases of integrated circuits is required to propel the electronics industry. Attention is turning to III-V compound semiconductors that are well positioned to replace silicon as the base material in logic switching devices. Their outstanding electron transport properties and the possibility to tune heterostructures provide tremendous opportunities to engineer novel nanometer-scale logic transistors. The scaling constraints require an evolution from planar III-V metal oxide semiconductor field-effect transistors (MOSFETs) toward transistor channels with a three-dimensional structure, such as nanowire FETs, to achieve future performance needs for complementary metal oxide semiconductor (CMOS) nodes beyond 10 nm. Further device innovations are required to increase energy efficiency. This could be addressed by tunnel FETs (TFETs), which rely on interband tunneling and thus require advanced III-V heterostructures for optimized performance. This article describes the challenges and recent progress toward the development of III-V MOSFETs and heterostructure TFETs—from planar to nanowire devices—integrated on a silicon platform to make these technologies suitable for future CMOS application

Modeling and optimization of Tunnel-FET architectures exploiting carrier gas dimensionality

The semiconductor industry, governed by the Moore's law, has achieved the almost unbelievable feat of exponentially increasing performance while lowering the costs for years. The main enabler for this achievement has been the scaling of the CMOS transistor that allowed the manufacturers to pack more and more functionality into the same chip area. However, it is now widely agreed that the happy days of scaling are well over and we are about to reach the physical limits of the CMOS concept. One major, insurmountable limit of CMOS is the so-called thermionic emission limit which dictates that the switching slope of the transistor cannot go below 60mV/dec at room temperature. This makes it impossible to scale down the supply voltage for CMOS transistor without dramatically increasing the static power consumption. To address this issue, a novel transistor concept called Tunnel FET (TFET) which utilizes the quantum mechanical band-to-band tunneling (BTBT) has been proposed. TFETs possess the potential to overcome the thermionic emission limit and therefore allow for low supply voltage operation. This thesis aims at investigating the performance of TFETs with alternative architectures exploiting quantized carrier gases through quantum mechanical simulations. To this end, 1D and 2D self-consistent Schrödinger-Poisson solvers with closed boundaries are developed along with the phonon-assisted and direct BTBT models implemented as a post-processing step. Moreover, we propose an efficient method to incorporate the quantization along the transverse direction which enables us to simulate different dimensionality combinations. The implemented models are calibrated against experimental and more fundamental quantum mechanical simulation methods such as k.p and tight-binding NEGF using tunneling diode structures. Using these tools, we simulate an advanced TFET architecture called electron-hole bilayer TFET (EHBTFET) which exploits BTBT between 2D electron and hole gases electrostatically induced by two separate oppositely biased gates. The subband-to-subband tunneling is first analyzed with the 1D simulator where the device working principle is demonstrated. Then, non-idealities of the EHBTFET operation such as the lateral tunneling and corner effects are investigated using the 2D simulator. The origin of the lateral leakage and techniques to reduce it are analyzed in detail. A parameter space analysis of the EHBTFET is performed by simulating a wide range of channel materials, channel thickness and oxide thicknesses. Our results indicate the possibility of having 2D-2D and 3D-3D tunneling for the EHBTFET, depending on the parameters chosen. A novel digital logic scheme utilizing the independent biasing property of the EHBTFET n- and p-gates is proposed and verified through quantum-corrected TCAD simulations. The performance benchmarking against a 28nm FD-SOI CMOS technology is performed as well. The results indicate that the EHBTFET logic can outperform the CMOS counterpart in the low supply voltage (subthreshold) regime, where it can offer significantly higher drive current due to its steep switching slope. We also compare the different dimensionality cases and highlight important differences between the face and edge tunneling devices in terms of their dependence on the device parameters (channel material, channel thickness and EOT)

A hierarchical optimization engine for nanoelectronic systems using emerging device and interconnect technologies

A fast and efficient hierarchical optimization engine was developed to benchmark and optimize various emerging device and interconnect technologies and system-level innovations at the early design stage. As the semiconductor industry approaches sub-20nm technology nodes, both devices and interconnects are facing severe physical challenges. Many novel device and interconnect concepts and system integration techniques are proposed in the past decade to reinforce or even replace the conventional Si CMOS technology and Cu interconnects. To efficiently benchmark and optimize these emerging technologies, a validated system-level design methodology is developed based on the compact models from all hierarchies, starting from the bottom material-level, to the device- and interconnect-level, and to the top system-level models. Multiple design parameters across all hierarchies are co-optimized simultaneously to maximize the overall chip throughput instead of just the intrinsic delay or energy dissipation of the device or interconnect itself. This optimization is performed under various constraints such as the power dissipation, maximum temperature, die size area, power delivery noise, and yield. For the device benchmarking, novel graphen PN junction devices and InAs nanowire FETs are investigated for both high-performance and low-power applications. For the interconnect benchmarking, a novel local interconnect structure and hybrid Al-Cu interconnect architecture are proposed, and emerging multi-layer graphene interconnects are also investigated, and compared with the conventional Cu interconnects. For the system-level analyses, the benefits of the systems implemented with 3D integration and heterogeneous integration are analyzed. In addition, the impact of the power delivery noise and process variation for both devices and interconnects are quantified on the overall chip throughput.Ph.D

Two-Dimensional Electronic Materials and Devices: Opportunities and Challenges

The unprecedented growth of the Internet of Things (IoT) and the 4th Industrial Revolution (Industry 4.0) not only demands dimensional scaling of device technologies but also new types of applications beyond today’s electronics. Two-dimensional (2D) materials, a group of layered crystals (such as graphene and MoS2) with unique properties, have emerged as promising candidates for IoT and Industry 4.0 since they can, not only extend the scaling with unprecedented performance and energy efficiency but also exhibit high potential for novel electronic devices. However, such nanomaterials suffer from significant challenges in process integration, especially in the modules that involves the formation of interfaces between 2D materials and conventional bulk materials. Thus, realizing high-performance energy-efficient 2D electronic devices has been challenging. This dissertation focuses on understanding the fundamental issues in such 2D materials (such as contacts, interfaces and doping) and in identifying applications uniquely enabled by these materials.First, a comprehensive treatment of metal contacts to 2D semiconductors, which has been a huge hurdle for 2D electronic technologies, will be presented. As a pioneering study, new interface physics originating from the unique dimensionality and surface properties have been revealed [1]. Solutions to minimize contact resistance are described though techniques of interface hybridization [2] and seamless contacts [3], [4]. These techniques transform 2D semiconductors from solely scientifically-interesting materials into high-performance field-effect transistor (FET) technologies, such as MoS2 FETs with record-low contact resistances [5], [6] and WSe2 FETs with record-high drive current and mobility [7]. Beyond metal interfaces, dielectric interface is crucial for preserving the carrier mobility in 2D channels, for which a solution enabled by buffer layers has been proposed [8]. On the other hand, the vertical van der Waals interfaces between 2D and 3D semiconductors, which retain the advantages of pristine ultra-thin 2D films as well as maximized tunneling area/field, have been studied and exploited into a novel beyond-silicon transistor technology – the first 2D channel tunnel FET (TFET) [9], which beat the fundamental limitation in the switching behavior of transistors. Recent results from the engineering of such 2D-3D semiconductor interfaces by surface reduction/passivation are described, showing a significant boost of drive current. While conventional diffusion/ion implantation methods are infeasible for 2D materials, two efficient doping techniques that are specific for 2D materials – surface doping [10], [11] and intercalation doping [12] are presented. The theoretical study of surface doping using ab-initio methods helped develop a novel doping scheme that uniquely exploits the Lewis-base like pedigree of 2D semiconductors without disturbing the structural integrity of the 2D atomic layer configuration [13], as well as a novel electrocatalyst based on MoS2 that achieved record high hydrogen evolution reaction (HER) performance [14]. On the other hand, intercalation doping has been employed to demonstrate graphene based transparent electrodes with the best combination of transmittance and sheet resistance [12], and also the first graphene interconnects with excellent performance, reliability and energy-efficiency [15], [16]. Moreover, by uniquely exploiting the high kinetic inductance and conductivity of intercalation doped graphene, a fundamentally different on-chip inductor has been demonstrated [17], [18], with both small form-factors and high inductance values, that were once thought unachievable in tandem. This 2D technique provides an attractive solution to the longstanding scaling problem of analog/radio-frequency electronics and opens up an unconventional pathway for the development of future ultra-compact wireless communication systems. Finally, a novel dissipative quantum transport methodology based on Büttiker probes with band-to-band tunneling capability is developed for 2D FETs [19]. Subsequently, gate-induced-drain-leakage (GIDL), one of the main leakage mechanisms in FETs especially access transistors, is evaluated for the first time for 2D FETs. The results establish the advantages of certain 2D semiconductors in greatly reducing GIDL and thereby support use of such materials in future memory technologies.The dissertation concludes with a vision for how a smart life can be realized in the future by harnessing the capabilities of various 2D technologies in the era of IoT and Industry 4.0.[1] J. Kang, D. Sarkar, W. Liu, D. Jena, and K. Banerjee, “A computational study of metal-contacts to beyond-graphene 2D semiconductor materials,” in IEEE International Electron Devices Meeting, 2012, pp. 407–410.[2] J. Kang, W. Liu, D. Sarkar, D. Jena, and K. Banerjee, “Computational Study of Metal Contacts to Monolayer Transition-Metal Dichalcogenide Semiconductors,” Phys. Rev. X, vol. 4, no. 3, p. 31005, Jul. 2014.[3] J. Kang, D. Sarkar, Y. Khatami, and K. Banerjee, “Proposal for all-graphene monolithic logic circuits,” Appl. Phys. Lett., vol. 103, no. 8, p. 83113, 2013.[4] A. Allain, J. Kang, K. Banerjee, and A. Kis, “Electrical contacts to two-dimensional semiconductors,” Nat. Mater., vol. 14, no. 12, pp. 1195–1205, 2015.[5] W. Liu et al., “High-performance few-layer-MoS2 field-effect-transistor with record low contact-resistance,” in IEEE International Electron Devices Meeting, 2013, pp. 499–502.[6] J. Kang, W. Liu, and K. Banerjee, “High-performance MoS2 transistors with low-resistance molybdenum contacts,” Appl. Phys. Lett., vol. 104, no. 9, p. 93106, Mar. 2014.[7] W. Liu, J. Kang, D. Sarkar, Y. Khatami, D. Jena, and K. Banerjee, “Role of metal contacts in designing high-performance monolayer n-type WSe2 field effect transistors.,” Nano Lett., vol. 13, no. 5, pp. 1983–90, May 2013.[8] J. Kang, W. Liu, and K. Banerjee, “Computational Study of Interfaces between 2D MoS2 and Surroundings,” in 45th IEEE Semiconductor Interface Specialists Conference, 2014.[9] D. Sarkar et al., “A subthermionic tunnel field-effect transistor with an atomically thin channel,” Nature, vol. 526, no. 7571, pp. 91–95, Sep. 2015.[10] Y. Khatami, W. Liu, J. Kang, and K. Banerjee, “Prospects of graphene electrodes in photovoltaics,” in Proceedings of SPIE, 2013, vol. 8824, p. 88240T–88240T–6.[11] D. Sarkar et al., “Functionalization of Transition Metal Dichalcogenides with Metallic Nanoparticles: Implications for Doping and Gas-Sensing,” Nano Lett., vol. 15, no. 5, pp. 2852–2862, May 2015.[12] W. Liu, J. Kang, and K. Banerjee, “Characterization of FeCl3 intercalation doped CVD few-layer graphene,” IEEE Electron Device Lett., vol. 37, no. 9, pp. 1246–1249, Sep. 2016.[13] S. Lei et al., “Surface functionalization of two-dimensional metal chalcogenides by Lewis acid–base chemistry,” Nat. Nanotechnol., vol. 11, no. 5, pp. 465–471, Feb. 2016.[14] J. Li, J. Kang, Q. Cai, W. Hong, C. Jian, and W. Liu, “Boosting Hydrogen Evolution Performance of MoS2 by Band Structure Engineering,” Adv. Mater. Interfaces, vol. 1700303, 2017.[15] J. Jiang et al., “Intercalation doped multilayer-graphene-nanoribbons for next-generation interconnects,” Nano Lett., vol. 17, no. 3, pp. 1482–1488, Mar. 2017.[16] J. Jiang, J. Kang, and K. Banerjee, “Characterization of Self - Heating and Current - Carrying Capacity of Intercalation Doped Graphene - Nanoribbon Interconnects,” in IEEE International Reliability Physics Symposium, 2017, p. 6B.1.1-6B.1.6.[17] X. Li et al., “Graphene inductors for high-frequency applications - design, fabrication, characterization, and study of skin effect,” in IEEE International Electron Devices Meeting, 2014, p. 5.4.1-5.4.4.[18] J. Kang et al., under review.[19] J. Kang et al., under review