A Survey Addressing on High Performance On-Chip VLSI Interconnect

With the rapid increase in transmission speeds of communication systems, the demand for very high-speed lowpower VLSI circuits is on the rise. Although the performance of CMOS technologies improves notably with scaling, conventional CMOS circuits cannot simultaneously satisfy the speed and power requirements of these applications. In this paper we survey the state of the art of on-chip interconnect techniques for improving performance, power and delay optimization and also comparative analysis of various techniques for high speed design have been discussed

Modeling and Analysis of Noise and Interconnects for On-Chip Communication Link Design

This thesis considers modeling and analysis of noise and interconnects in onchip communication. Besides transistor count and speed, the capabilities of a modern design are often limited by on-chip communication links. These links typically consist of multiple interconnects that run parallel to each other for long distances between functional or memory blocks. Due to the scaling of technology, the interconnects have considerable electrical parasitics that affect their performance, power dissipation and signal integrity. Furthermore, because of electromagnetic coupling, the interconnects in the link need to be considered as an interacting group instead of as isolated signal paths. There is a need for accurate and computationally effective models in the early stages of the chip design process to assess or optimize issues affecting these interconnects. For this purpose, a set of analytical models is developed for on-chip data links in this thesis. First, a model is proposed for modeling crosstalk and intersymbol interference. The model takes into account the effects of inductance, initial states and bit sequences. Intersymbol interference is shown to affect crosstalk voltage and propagation delay depending on bus throughput and the amount of inductance. Next, a model is proposed for the switching current of a coupled bus. The model is combined with an existing model to evaluate power supply noise. The model is then applied to reduce both functional crosstalk and power supply noise caused by a bus as a trade-off with time. The proposed reduction method is shown to be effective in reducing long-range crosstalk noise. The effects of process variation on encoded signaling are then modeled. In encoded signaling, the input signals to a bus are encoded using additional signaling circuitry. The proposed model includes variation in both the signaling circuitry and in the wires to calculate the total delay variation of a bus. The model is applied to study level-encoded dual-rail and 1-of-4 signaling. In addition to regular voltage-mode and encoded voltage-mode signaling, current-mode signaling is a promising technique for global communication. A model for energy dissipation in RLC current-mode signaling is proposed in the thesis. The energy is derived separately for the driver, wire and receiver termination.Siirretty Doriast

Microwave Package Design for Superconducting Quantum Processors

Solid-state qubits with transition frequencies in the microwave regime, such as superconducting qubits, are at the forefront of quantum information processing. However, high-fidelity, simultaneous control of superconducting qubits at even a moderate scale remains a challenge, partly due to the complexities of packaging these devices. Here, we present an approach to microwave package design focusing on material choices, signal line engineering, and spurious mode suppression. We describe design guidelines validated using simulations and measurements used to develop a 24-port microwave package. Analyzing the qubit environment reveals no spurious modes up to 11GHz. The material and geometric design choices enable the package to support qubits with lifetimes exceeding 350 {\mu}s. The microwave package design guidelines presented here address many issues relevant for near-term quantum processors.Comment: 15 pages, 9 figure

Hardware and Methods for Scaling Up Quantum Information Experiments

Quantum computation promises to solve presently intractable problems, with hopes of yielding solutions to pressing issues to society. Despite this, current machines are limited to tens of qubits. The field is in a state of continuous scaling, with groups around the world working on all aspects of this problem. The work of this thesis aims to contribute to this effort. It is motivated by the goal of increasing both the speed and bandwidth of experiments conducted within our laboratory. Low-loss radio-frequency multiplexers were characterised at cryogenic temperatures, with some shown to operate at below 7mK. The Analog Devices ADG904 was one of these, and its insertion loss was measured at <0.5dB up to 2GHz. Their heat load was measured, and it was found that a switching speed of 10 MHz with an RF signal power of -30dB dissipates 43uW. Installing these switches yields a benefit over installing extra cabling in our cryostat for a switching speed of up to 2MHz and RF power of -30dBm. A switch matrix was prototyped for cryogenic operation, enabling re-routing of wiring inside a cryostat with a minimally increased thermal load. This could be used to significantly increase the scale of high frequency experiments. This switch has also been embedded within a calibration routine, facilitating measurement of a specific feature of interest at millikelvin temperatures. As the field of quantum engineering scales, such measurements will be crucial to close the loop, providing feedback to fabrication and semiconductor growth efforts. Finally, a rapid-turnaround test rig has been developed which has 32 high frequency and 100 DC lines, enabling tests of significant scale in liquid helium. This reduces the time per experiment at 4.2 K to hours rather than days, enabling tests such as thermal cycling, as well as the evaluation of on-chip structures or active electronics and classical computing hardware; which are all necessary elements of any solid state quantum computing architecture

RF and Microwave Measurements

open1noBasic theory and techniques are concentrated mostly in the first four chapters, where definitions, formulas and references are collected aiming at giving a thorough overview of the most relevant topics: circuit theory, material properties, transmission lines, signal analysis and spectral analysis, including random processes, probability and statistics. The central chapters 5, 6 and 7 deals with three important elements of setups and experiments: cables, printed circuit boards and connectors. The influence on the overall measurement, their modeling and characterization are discussed, keeping an eye on applicable standards. The last four chapters cover advanced aspects of scattering parameters, differential lines and mixed modes, and the use and performance of spectrum analyzer and vector network analyzer.openA. MariscottiMariscotti, A

Static noise margin analysis for CMOS logic cells in near-threshold

The advancement of semiconductor technology enabled the fabrication of devices with faster switching activity and chips with higher integration density. However, these advances are facing new impediments related to energy and power dissipation. Besides, the increasing demand for portable devices leads the circuit design paradigm to prioritize energy efficiency instead of performance. Altogether, this scenario motivates engineers towards reducing the supply voltage to the near and subthreshold regime to increase the lifespan of battery-powered devices. Even though operating in these regime offer interesting energy-frequency trade-offs, it brings challenges concerning noise tolerance. As the supply voltage reduces, the available noise margins decrease, and circuits become more prone to functional failures. In addition, near and subthreshold circuits are more susceptible to manufacturing variability, hence further aggravating noise issues. Other issues, such as wire minimization and gate fan-out, also contribute to the relevance of evaluating the noise margin of circuits early in the design Accordingly, this work investigates how to improve the static noise margin of digital synchronous circuits that will operate at the near/subthreshold regime. This investigation produces a set of three original contributions. The first is an automated tool to estimate the static noise margin of CMOS combinational cells. The second contribution is a realistic static noise margin estimation methodology that considers process-voltage-temperature variations. Results show that the proposed methodology allows to reduce up to 70% of the static noise margin pessimism. Finally, the third contribution is the noise-aware cell design methodology and the inclusion of a noise evaluation of complex circuits during the logic synthesis. The resulting library achieved higher static noise margin (up to 24%) and less spread among different cells (up to 62%).Os avanços na tecnologia de semicondutores possibilitou que se fabricasse dispositivos com atividade de chaveamento mais rápida e com maior capacidade de integração de transistores. Estes avanços, todavia, impuseram novos empecilhos relacionados com a dissipação de potência e energia. Além disso, a crescente demanda por dispositivos portáteis levaram à uma mudança no paradigma de projeto de circuitos para que se priorize energia ao invés de desempenho. Este cenário motivou à reduzir a tensão de alimentação com qual os dispositivos operam para um regime próximo ou abaixo da tensão de limiar, com o objetivo de aumentar sua duração de bateria. Apesar desta abordagem balancear características de performance e energia, ela traz novos desafios com relação a tolerância à ruído. Ao reduzirmos a tensão de alimentação, também reduz-se a margem de ruído disponível e, assim, os circuitos tornam-se mais suscetíveis à falhas funcionais. Somado à este efeito, circuitos com tensões de alimentação nestes regimes são mais sensíveis à variações do processo de fabricação, logo agravando problemas com ruído. Existem também outros aspectos, tais como a miniaturização das interconexões e a relação de fan-out de uma célula digital, que incentivam a avaliação de ruído nas fases iniciais do projeto de circuitos integrados Por estes motivos, este trabalho investiga como aprimorar a margem de ruído estática de circuitos síncronos digitais que irão operar em tensões no regime de tensão próximo ou abaixo do limiar. Esta investigação produz um conjunto de três contribuições originais. A primeira é uma ferramenta capaz de avaliar automaticamente a margem de ruído estática de células CMOS combinacionais. A segunda contribuição é uma metodologia realista para estimar a margem de ruído estática considerando variações de processo, tensão e temperatura. Os resultados obtidos mostram que a metodologia proposta permitiu reduzir até 70% do pessimismo das margens de ruído estática, Por último, a terceira contribuição é um fluxo de projeto de células combinacionais digitais considerando ruído, e uma abordagem para avaliar a margem de ruído estática de circuitos complexos durante a etapa de síntese lógica. A biblioteca de células resultante deste fluxo obteve maior margem de ruído (até 24%) e menor variação entre diferentes células (até 62%)