Through Silicon Via의 Coupling Noise를 억제하는 반전 전하층을 이용한 Guard Ring 제작 및 분석

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2015. 8. 이종호.As technology shrinks, the implementation of high-density chip with a two-dimensional (2-D) planar architecture is becoming more difficult due to the limitation of lithography process. To overcome such scale-down limitations, a three-dimensional (3-D) package has been investigated. Among the various 3-D package technologies, a through silicon via (TSV) is a promising technology in which several chips are stacked vertically and electrically. This 3-D package can enhance the memory capacity, and implement a system with different functional chips. Although TSVs offer many advantages when used to achieve a high-density package, they also have several disadvantages, such as coupling noise. A high-frequency signal applied to a TSV induces noise in transistors near the TSV due to electrical coupling. Another issue is that copper (Cu) which is used as a conducting material of the TSV generates trap density caused by large diffusivity of Cu atoms. In this dissertation, we propose a new guard ring which consists of a shallow n+ region, a deep n-well, and an inversion layer formed along the interface between the oxide surrounding the TSV (TSV oxide) and the p-substrate. The proposed guard ring utilizes an inversion charge induced by a positive oxide charge located at the interface of the TSV oxide. We characterize quantitatively a TSV with a guard ring which is used to reduce the coupling noise from the TSV by utilizing an inversion layer as a shield layer. It is shown that a transient current due to the coupling is clearly reduced when the proposed guard ring is used. The proposed method is compared with a conventional guard ring method in terms of the drain current of a victim nMOSFET. The effective depth of the inversion layer with the signal frequency is also characterized. It is demonstrated that the high-frequency response of the guard ring can be modeled as an RC equivalent circuit. The proposed guard ring is effective in shielding the coupling noise and can be fabricated easily by modifying the ion implantation mask layer. A TSV conducting material requires high conductivity for low power consumption and high-speed operation. Cu is widely used as a TSV conducting material, but Cu atoms diffuse to the adjacent silicon substrate and transistors easily and generate traps during a low temperature annealing process. It is very important to suppress Cu diffusion and to devise a proper method to measure how many Cu atoms diffuse due to annealing. However, the characteristics of traps induced by Cu diffusion in a TSV are not easily measured because TSVs are typically located some distance away from the silicon surface, reaching a depth of tens of micrometers. For this reason, the deep part of a TSV cannot be measured. We suggest a measurement method which can be used to evaluate the trap density generated by Cu diffusion through the use of the proposed guard ring and analyze Cu diffusion as a parameter of the thickness of the barrier metal.Contents Abstract 1 Contents 4 Chapter 1 Introduction 6 1.1 BACKGROUND OF TSV 6 1.2 MOTIVATION FOR THE RESEARCH 14 Chapter 2 Structure of the guard ring and the TSV 15 2.1 INTRODUCTION 15 2.2 PROCESS FLOW OF FABRICATING TSV AND GUARD RING 20 2.3 STRUCTURE OF THE TSV AND THE PROPOSED GUARD RING 24 Chapter 3 Characteristics of the proposed guard ring 27 3.1 INTRODUCTION 27 3.2 JUNCTION CHARACTERISTICS OF THE PROPOSED GUARD RING 28 3.3 C-V CHARACTERISTICS OF THE PROPOSED GUARD RING 31 Chapter 4 Effective method to analyze the trap density 40 4.1 INTRODUCTION 40 4.2 CHARACTERISTICS OF CU DIFFUSION WITH BARRIER METAL THICKNESS 42 4.3 EFFECT OF CU DIFFUSION ENHANCED BY ADDITIONAL ANNEALING 53 Chapter 5 Shielding ability of the proposed guard ring 65 5.1 INTRODUCTION 65 5.2 SHIELDING ABILITY OF THE PROPOSED GUARD RING 69 5.3 EFFECTIVENESS OF THE PROPOSED GUARD RING 75 5.4 CHARACTERISTICS OF THE PROPOSED GUARD RING BY RC MODELING 86 Conclusions 91 Bibliography 93 Abstract in Korean 98Docto

Optimisation de la gravure de macropores ordonnés dans le silicium et de leur remplissage de cuivre par voie électrochimique (application aux via traversants conducteurs)

Ces travaux de thèse portent sur la fabrication de via traversants conducteurs, brique technologique indispensable pour l intégration des composants microélectroniques en 3 dimensions. Pour ce faire, une voie tout-électrochimique a été explorée en raison de son faible coût de fabrication par rapport aux techniques par voie chimique sèche. Ainsi, la gravure de macropores ordonnés traversants a été réalisée par anodisation du silicium en présence d acide fluorhydrique puis leur remplissage de cuivre par dépôt électrochimique. L objectif est de faire du silicium macroporeux une alternative crédible à la gravure sèche (DRIE) pour la structuration du silicium.Les conditions de gravure de matrices de macropores ordonnés traversants ont été étudiées à la fois dans des substrats silicium de type n et p faiblement dopés. La composition de l électrolyte ainsi que le motif des matrices ont été optimisés afin de garantir la gravure de via traversants de forte densité et à facteur de forme élevé. Une fois gravés, les via traversant ont été remplis de cuivre. En optimisant ces paramètres une résistance minimale égale à 32 m /via (soit 1,06 fois la résistivité théorique du cuivre à 20C) a été mesurée.These thesis works deal with the achievement of Through Silicon Via (TSV) essential technological issue for microelectronic device 3D integration. For this purpose, we opted for a full-electrochemical way of TSV production because of lower fabrication costs as compared to dry etching and deposition techniques. Indeed, ordered through silicon macropores were carried out by silicon anodization in hydrofluoric acid-containing solution and then filled by copper electrochemical deposition. The main objective is to determine if the macroporous silicon arrays can be a viable alternative as Deep Reactive Ion Etching (DRIE).The etching parameters of through silicon macropore arrays were studied both in low-doped n- and p-type silicon. The electrolyte composition as well as the density of the initiation sites was optimized to enable the growth of high aspect ratio, high density through silicon ordered macropores. After silicon anodization, through via were filled with copper. By optimizing the copper deposition parameters (bath composition and applied potential), the resistance per via was measured equal to 32 m (i.e. 1.06 times higher than the theoretical copper bulk resistivity).TOURS-Bibl.électronique (372610011) / SudocSudocFranceF