The impact of self-heating and SiGe strain-relaxed buffer thickness on the analog performance of strained Si nMOSFETs

The impact of the thickness of the silicon–germanium strain-relaxed buffer (SiGe SRB) on the analog performance of strained Si nMOSFETs is investigated. The negative drain conductance caused by self-heating at high power levels leads to negative self-gain which can cause anomalous circuit behavior like non-linear phase shifts. Using AC and DC measurements, it is shown that reducing the SRB thickness improves the analog design space and performance by minimizing self-heating. The range of terminal voltages that leverage positive self-gain in 0.1 μm strained Si MOSFETs fabricated on 425 nm SiGe SRBs is increased by over 100% compared with strained Si devices fabricated on conventional SiGe SRBs 4 μm thick. Strained Si nMOSFETs fabricated on thin SiGe SRBs also show 45% improvement in the self-gain compared with the Si control as well as 25% enhancement in the on-state performance compared with the strained Si nMOSFETs on the 4 μm SiGe SRB. The extracted thermal resistance is 50% lower in the strained Si device on the thin SiGe SRB corresponding to a 30% reduction in the temperature rise compared with the device fabricated on the 4 μm SiGe SRB. Comparisons between the maximum drain voltages for positive self-gain in the strained Si devices and the ITRS projections of supply-voltage scaling show that reducing the thickness of the SiGe SRB would be necessary for future technology nodes

III-V and 2D Devices: from MOSFETs to Steep-Slope Transistors

With silicon CMOS technology approaching the scaling limit, alternating channel materials and novel device structures have been extensively studied and attracted a lot of attention in solid-state device research. In this dissertation, solid-state electron devices for post-Si CMOS applications are explored including both new materials such as III-V and 2D materials and new device structures such as tunneling field-effect transistors and negative capacitance field-effect transistors. Multiple critical challenges in applying such new materials and new device structures are addressed and the key achievements in this dissertation are summarized as follows: 1) Development of fabrication process technology for ultra-scaled planar and 3D InGaAs MOSFETs. 2) Interface passivation by forming gas anneal on InGaAs gate-all-around MOSFETs. 3) Characterization methods for ultra-scaled MOSFETs, including a correction to subthreshold method and low frequency noise characterization in short channel devices. 4) Development of short channel InGaAs planar and 3D gate-allaround tunneling field-effect transistors. 5) Negative capacitance field-effect transistors with hysteresis-free and bi-directional sub-thermionic subthreshold slope and the integration with various channel materials such as InGaAs and MoS2

Characterization and modeling of low-frequency noise in Hf-based high -kappa dielectrics for future cmos applications

The International Technology Roadmap for Semiconductors outlines the need for high-K dielectric based gate-oxide Metal Oxide Semiconductor Field Effect Transistors for sub-45 nm technology nodes. Gate oxides of hafnium seem to be the nearest and best alternative for silicon dioxide, when material, thermal and structural properties are considered. Usage of poly-Si as a gate electrode material degrades the performance of the device and hence gate stacks based on metal gate electrodes are gaining high interest. Though a substantial improvement in the performance has been achieved with these changes, reliability issues are a cause of concern. For analog and mixed-signal applications, low-frequency (I /f~ noise is a major reliability factor. Also in recent years. low frequency noise diagnostics has become a powerful tool for device performance and reliability characterization. This dissertation work demonstrates the necessity of gate stack engineering for achieving a low I/f noise performance. Changes in the material and process parameters of the devices, impact the 1/f noise behavior. The impact of 1/f noise on gate technology and processing parameters xvere identified and investigated. The thickness and the quality of the interfacial oxide, the nitridation effects of the layers, high-K oxide, bulk properties of the high-K layer. percentage of hafnium content in the high-K, post deposition anneal (PDA) treatments, effects of gate electrode material (poly-silicon. fully silicided or metal). Gate electrode processing are investigated in detail. The role of additional interfaces and bulk layers of the gate stack is understood. The dependence of low-frequency noise on high and low temperatures was also investigated. A systematic and a deeper understanding of these parameters on 1/f noise behavior are deduced which also forms the basis for improved physics-based 1/f noise modeling. The model considers the effect of the interfacial layer and also temperature, based on tunneling based thermally activated model. The simulation results of improved drain-current noise model agree well with the experimentally calculated values

Compact modelling in RF CMOS technology

With the continuous downscaling of complementary metal-oxide-semiconductor (CMOS) technology, the RF performance of metal-oxide-semiconductor field transistors (MOSFETs) has considerably improved over the past years. Today, the standard CMOS technology has become a popular choice for realizing radio frequency (RF) applications. The focus of the thesis is on device compact modelling methodologies in RF CMOS. Compact models oriented to integrated circuit (ICs) computer automatic design (CAD) are the key component of a process design kit (PDK) and the bridge between design houses and foundries. In this work, a novel substrate model is proposed for accurately characterizing the behaviour of RF-MOSFETs with deep n-wells (DNW). A simple test structure is presented to directly access the substrate parasitics from two-port measurements in DNWs. The most important passive device in RFIC design in CMOS is the spiral inductor. A 1-pi model with a novel substrate network is proposed to characterize the broadband loss mechanisms of spiral inductors. Based on the proposed 1-pi model, a physics-originated fully-scalable 2-pi model and model parameter extraction methodology are also presented for spiral inductors in this work. To test and verify the developed active and passive device models and model parameter extraction methods, a series of RF-MOSFETs and planar on-chip spiral inductors with different geometries manufactured by employing standard RF CMOS processes were considered. Excellent agreement between the measured and the simulated results validate the compact models and modelling technologies developed in this work

An investigation on border traps in III-V MOSFETs with an In0.53Ga0.47As channel

Continuing CMOS performance scaling requires developing MOSFETs of high-mobility semiconductors and InGaAs is a strong candidate for n-channel. InGaAs MOSFETs, however, suffer from high densities of border traps, and their origin and impact on device characteristics are poorly understood at present. In this paper, the border traps in nMOSFETs with an In0.53Ga0.47As channel and Al2O3 gate oxide are investigated using the discharging-based energy profiling technique. By analyzing the trap energy distributions after charging under different gate biases, two types of border traps together with their energy distributions are identified. Their different dependences on temperature and charging time support that they have different physical origins. The impact of channel thickness on them is also discussed. Identifying and understanding these different types of border traps can assist in the future process optimization. Moreover, border trap study can yield crucial information for long-term reliability modeling and device timeto-failure projection

Simulation of charge-trapping in nano-scale MOSFETs in the presence of random-dopants-induced variability

The growing variability of electrical characteristics is a major issue associated with continuous downscaling of contemporary bulk MOSFETs. In addition, the operating conditions brought about by these same scaling trends have pushed MOSFET degradation mechanisms such as Bias Temperature Instability (BTI) to the forefront as a critical reliability threat. This thesis investigates the impact of this ageing phenomena, in conjunction with device variability, on key MOSFET electrical parameters. A three-dimensional drift-diffusion approximation is adopted as the simulation approach in this work, with random dopant fluctuations—the dominant source of statistical variability—included in the simulations. The testbed device is a realistic 35 nm physical gate length n-channel conventional bulk MOSFET. 1000 microscopically different implementations of the transistor are simulated and subjected to charge-trapping at the oxide interface. The statistical simulations reveal relatively rare but very large threshold voltage shifts, with magnitudes over 3 times than that predicted by the conventional theoretical approach. The physical origin of this effect is investigated in terms of the electrostatic influences of the random dopants and trapped charges on the channel electron concentration. Simulations with progressively increased trapped charge densities—emulating the characteristic condition of BTI degradation—result in further variability of the threshold voltage distribution. Weak correlations of the order of 10-2 are found between the pre-degradation threshold voltage and post-degradation threshold voltage shift distributions. The importance of accounting for random dopant fluctuations in the simulations is emphasised in order to obtain qualitative agreement between simulation results and published experimental measurements. Finally, the information gained from these device-level physical simulations is integrated into statistical compact models, making the information available to circuit designers

Compact Models for Integrated Circuit Design

This modern treatise on compact models for circuit computer-aided design (CAD) presents industry standard models for bipolar-junction transistors (BJTs), metal-oxide-semiconductor (MOS) field-effect-transistors (FETs), FinFETs, and tunnel field-effect transistors (TFETs), along with statistical MOS models. Featuring exercise problems at the end of each chapter and extensive references at the end of the book, the text supplies fundamental and practical knowledge necessary for efficient integrated circuit (IC) design using nanoscale devices. It ensures even those unfamiliar with semiconductor physics gain a solid grasp of compact modeling concepts

Characterization of high-k layers as the gate dielectric for MOSFETs

As the gate oxide thickness of the Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) is continuously scaled down with lateral device dimensions, the gate leakage current during operation increases exponentially. This increase in leakage current raises concerns regarding power consumption and device reliability. Alternative dielectrics with higher dielectric constant (high-k) than that of Si02 have been searched. High-k layers allow the use of physically thicker gate dielectrics, so that the gate leakage current is controlled. The intensive world-wide research has identified the Hf-dielectric as the lead candidate for future CMOS technologies. However, the commercial application of Hf-dielectrics as the gate oxide has been held back by a number of issues, including process integration, low carrier mobility, and high instability. This project focuses on characterizing the defect responsible for the instability of Hf-dielectrics. The thesis consists of six chapters. After an introduction in Chapter 1, the characterization techniques used are described in Chapter 2. Two main contributions are: setting up the pulse transfer characteristic technique and developing a newly improved charge pumping technique called Variable T charged is charge Pumping (VT2CP). The research results are presented in Chapters 3,4 and 5. Chapter 3 characterizes a s-grown electron traps in HfO2/SiO2s tacks. The issues addressed include the impact of measurement technique on electron trapping, contribution of different current components to trapping, trap location, and the capture cross section and trapping kinetics. It is shown that the use of pulse transfer characteristic technique is essential for measuring electron trapping, since the traditional quasi-dc transfer characteristic is too IV ABSTRACT slow and the loss of charges is significant. The trap assisted tunneling and the thermally enhanced conduction contributes little to trapping. The trapping does not pile up at the interfaces and the region near to one or both ends of Hf02 has little trapping, when compared with the trapping in the bulk. To evaluate the electron fluency through the gate stack, efforts are made to estimate the trapping-induced transient gate current through simulation. This allows the determination of two capture cross sections: one in the order of 10-14cma2n d the other in the order of 10-16cm2. Chapter 4 concentrates on the characterization of generated electron traps and the time dependent dielectric breakdown (TDDB). Amplitude charge pumping and frequency sweep charge pumping are used to investigate the impact of gate electrodes and channel length on charging and discharging of the bulk defects. As channel length increases,it is found that bulk trapping increases and TDDB time shortens. Efforts are made to show that there is a quantitative correlation between the trapping and TDDB data. The newly improved VTZCP is used to separate trapping in the interfacial Si02 from that in Hf02. The results show that new traps are generated in both layers and the generation follows a power law with similar power factors. Investigation is also carried out to assess the dependence of trap generation on process and deposition conditions. Finally, it is found that Hf-dielectric with metal gate always suffers hard-breakdown. In Chapter 5, attention is turned to positive charging in Hf-dielectric. It is shown that the use of metal gate enhances the positive charging, when stressed under a positive gate bias. This is explained by assuming that there is a large number of hydrogenous species within the metal gate or at its interface with gate dielectric. Two types of threshold voltage instabilities have been identified for pMOSFETs. The first one results in a loop in the transfer characteristics when a pulse is applied to the gate. The second one is caused by the generation of new positive charge. Both are enhanced by V ABSTRACT nitridation. For sub-2nm Hf-dielectric, the threshold voltage instability of pMOSFETs can be more severe than that of nMOSFETs and it can be a limiting factor for the operation voltage. Finally, the project is summarized in Chapter 6 and the future work is discussed