Comparative analysis of VDMOS/LDMOS power transistors for RF amplifiers

A comparison between the RF performance of vertical and lateral power MOSFETs is presented. The role of each parasitic parameter in the assessment of the power gain, 1-dB compression point, efficiency, stability, and output matching is evaluated quantitatively using new analytical expressions derived from a ten-element model. This study reveals that the contribution of the parasitic parameter on degradation of performance depends upon the specific technology and generic perceptions of source inductance and feedback capacitance in VDMOS degradation may not always hold. This conclusion is supported by a detailed analysis of three devices of the same power rating from three different commercial vendors. A methodology for optimizing a device technology, specifically for RF performance and power amplifier performance is demonstrated

A Survey of Non-conventional Techniques for Low-voltage Low-power Analog Circuit Design

Designing integrated circuits able to work under low-voltage (LV) low-power (LP) condition is currently undergoing a very considerable boom. Reducing voltage supply and power consumption of integrated circuits is crucial factor since in general it ensures the device reliability, prevents overheating of the circuits and in particular prolongs the operation period for battery powered devices. Recently, non-conventional techniques i.e. bulk-driven (BD), floating-gate (FG) and quasi-floating-gate (QFG) techniques have been proposed as powerful ways to reduce the design complexity and push the voltage supply towards threshold voltage of the MOS transistors (MOST). Therefore, this paper presents the operation principle, the advantages and disadvantages of each of these techniques, enabling circuit designers to choose the proper design technique based on application requirements. As an example of application three operational transconductance amplifiers (OTA) base on these non-conventional techniques are presented, the voltage supply is only ±0.4 V and the power consumption is 23.5 µW. PSpice simulation results using the 0.18 µm CMOS technology from TSMC are included to verify the design functionality and correspondence with theory

CMOS MESFET Cascode Amplifiers for RFIC Applications

abstract: There is an ever-increasing demand for higher bandwidth and data rate ensuing from exploding number of radio frequency integrated systems and devices. As stated in the Shannon-Hartley theorem, the maximum achievable data rate of a communication channel is linearly proportional to the system bandwidth. This is the main driving force behind pushing wireless systems towards millimeter-wave frequency range, where larger bandwidth is available at a higher carrier frequency. Observing the Moor’s law, highly scaled complementary metal–oxide–semiconductor (CMOS) technologies provide fast transistors with a high unity power gain frequency which enables operating at millimeter-wave frequency range. CMOS is the compelling choice for digital and signal processing modules which concurrently offers high computation speed, low power consumption, and mass integration at a high manufacturing yield. One of the main shortcomings of the sub-micron CMOS technologies is the low breakdown voltage of the transistors that limits the dynamic range of the radio frequency (RF) power blocks, especially with the power amplifiers. Low voltage swing restricts the achievable output power which translates into low signal to noise ratio and degraded linearity. Extensive research has been done on proposing new design and IC fabrication techniques with the goal of generating higher output power in CMOS technology. The prominent drawbacks of these solutions are an increased die area, higher cost per design, and lower overall efficiency due to lossy passive components. In this dissertation, CMOS compatible metal–semiconductor field-effect transistor (MESFETs) are utilized to put forward a new solution to enhance the power amplifier’s breakdown voltage, gain and maximum output power. Requiring no change to the conventional CMOS process flow, this low cost approach allows direct incorporation of high voltage power MESFETs into silicon. High voltage MESFETs were employed in a cascode structure to push the amplifier’s cutoff frequency and unity power gain frequency to the 5G and K-band frequency range. This dissertation begins with CMOS compatible MESFET modeling and fabrication steps, and culminates in the discussion of amplifier design and optimization methodology, parasitic de-embedding steps, simulation and measurement results, and high resistivity RF substrate characterization.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

Low-Voltage Ultra-Low-Power Current Conveyor Based on Quasi-Floating Gate Transistors

The field of low-voltage low-power CMOS technology has grown rapidly in recent years; it is an essential prerequisite particularly for portable electronic equipment and implantable medical devices due to its influence on battery lifetime. Recently, significant improvements in implementing circuits working in the low-voltage low-power area have been achieved, but circuit designers face severe challenges when trying to improve or even maintain the circuit performance with reduced supply voltage. In this paper, a low-voltage ultra-low-power current conveyor second generation CCII based on quasi-floating gate transistors is presented. The proposed circuit operates at a very low supply voltage of only ±0.4 V with rail-to-rail voltage swing capability and a total quiescent power consumption of mere 9.5 µW. Further, the proposed circuit is not only able to process the AC signal as it's usual at quasi-floating gate transistors but also the DC which extends the applicability of the proposed circuit. In conclusion, an application example of the current-mode quadrature oscillator is presented. PSpice simulation results using the 0.18 µm TSMC CMOS technology are included to confirm the attractive properties of the proposed circuit

Designing and Simulation of Various Class-F Radio-Frequency Power Amplifier

In this thesis, the various kinds of Class-F radio frequency power amplifiers are discussed. The Class-F3 RFPA is the one which has been designed and analyzed. It consists of an RF choke, blocking capacitor and a loading network. The loading network consists of a tank circuit resonating at fundamental operating frequency and also a parallel resonator circuit tuned to third harmonic. For a better understanding of the operation of Class-F3 amplifier, we go back to Class-C amplifier and discuss it briefly. Here the design remains same, operating at conduction angles less than 180 degree. The design equations were used to derive required circuit parameters on MATLAB. The designed circuit is implemented on SABER circuit simulator and resulting waveforms and frequency spectrums are also presented. The dependence of Class-F3 operation on gate-to-source voltage of a MOSFET is presented by varying it and showing the changes in the drain-to-source voltage and drain current. The frequency spectrum helps understand the harmonics in both signals. A design of the Class-F3 RFPA is presented with drain-source capacitance. A design for Class-F3 amplifier was produced where the MOSFET is forced to work in linear operating region and it is simulated in SABER. The plotted SABER simulation results are in agreement with the theoretically derived results. The simulated circuit efficiencies are a little less than what was calculated theoretically. The spectrums help clarify the results obtained

Design of a Class-D RF power amplifier in CMOS technology

In this thesis an RF Class-D Power Amplifier is presented. The analysis of the Class-D amplifier considering ideal components has shown that the drain efficiency of 100% can be achieved. The output power and the drain efficiency are degraded by the internal resistance of each component. A driver is used to drive the gate capacitances of the Class-D amplifier. Both driver and amplifier are implemented with CMOS inverters. The size of the inverters in the driver is scaled down by a factor of 3 relatively to the preceding stage. The first being the inverter of the Class-D amplifier. At the output a 3rd order Butterworth bandpass filter is implemented. A non-ideal analysis of the Class-D amplifier is performed to create a base model which is used to aid in the design of the circuit. The RF Class-D Power Amplifier with the operation frequency of 2.4GHz was implemented with standard 130 nm CMOS technology. Two simulations were taken into account considering ideal and pre-layout components in the output filter. The following results were obtained when using ideal components: the output power of 6.91 dBm, the drain efficiency of 40% and the overall efficiency of 23%. Using pre-layout components the results were the following: the output power of 0.317 dBm the drain and overall efficiency of 8.6% and 4.9%, respectively

Physics and technologies of silicon LDMOSFET for radio frequency applications

This thesis is devoted to the investigation of devices and technologies of Lateral Double-Diffused- Metal-Oxide-Semiconductor-Field-Effect-Transistor for Radio Frequency (RP) applications. Theoretical analysis and extensive 2-D process and device simulation results are presented. Theoretical analysis and simulations are carried out on RESURF LDMOS in both bulk and SOI substrate in terms of breakdown characteristics, transconductance, on resistance and CV characteristics. Quasi-saturation is a common phenomenon in DMOS devices. In this work, the dependence of quasi-saturation current on device physical and geometrical parameters is investigated in SOI RP LDMOS. Physical insight is gained into quasi-saturation on SOI RP LDMOS with different top silicon thickness and the same drift dose. It reveals that the difference in thick and thin film SOI lies in the different potential drop in the drift region. The influence of RESURF effect on quasi-saturation is also presented. It is shown that quasi-saturation current level can be affected by RESURF due to its influence on the drift dose. The mechanism of self-heating is presented and the influence of top silicon thickness, buried oxide thickness, voltage bias is studied through simulations. The change of peak temperature and its location with bias is due to the shift of electric field with voltage bias. A back-etch structure and fabrication process have been proposed to achieve a superior thermal performance. The negative differential conductance is not present in the non-isothermal IV curves. The temperature rise in the back-etch structure is less than 114 of that in the bulk structure. An RP LDMOS with a step drift doping profile on SIMOX substrate is evaluated. The fabrication process for the drift formation is proposed. The presented results demonstrate that step drift device has higher breakdown voltage than the conventional uniformly doped (UD) device, which provides the possibility to integrate LDMOS with low voltage CMOS for 28V base station application. This structure also has the advantage of suppressed kink effect due to the reduced electric field within the drift region. The step drift structure also features lower capacitance, improved drain current saturation behaviour and reduced self-heating at class AB bias point. For the first time, a novel sandwich structure for lateral RF MOSFET has been analysed based on silicon-on-nothing (SON) technology. The influence of device parameters on BV, CV and thermal performance has been investigated. Partial SON structure is found preferable in terms of heat conduct ability. Comparison on the electrical and thermal performance is made between SON LDMOSFET and conventional SOI alternative with BV of 40V. It is found that SON structure shows improvement in output capacitance and substrate loss. However, the temperature rise in SON device is higher compared to SOI alternative. The performance of the proposed sandwich SON structure has also been investigated in 28V base station applications, which requires breakdown voltage of 80V

An Ultra-Low-Power Track-and-Hold Amplifier

The future of electronics is the Internet of Things (IoT) paradigm, where always-on devices and sensors monitor and transform everyday life. A plethora of applications (such as navigating drivers past road hazards or monitoring bridge and building stresses) employ this technology. These unattended ground-sensor applications require decade(s)-long operational life-times without battery changes. Such electronics demand stringent performance specifications with only nano-Watt power levels.This thesis presents an ultra-low-power track-and-hold amplifier for such systems. It serves as the front-end of a SAR-ADC or the building block for equalizers or filters. This amplifier\u27s design attains exceptional hold times by mitigating switch subthreshold leakage and bulk leakage. Its novel transmission-gate topology achieves wide-swing performance. Though only consuming 100 pico-Watts, it achieves a precision of 7.6 effective number of bits (ENOB). The track-and-hold amplifier was designed in 130-nm CMOS