Modeling high-performance wormhole NoCs for critical real-time embedded systems

Manycore chips are a promising computing platform to cope with the increasing performance needs of critical real-time embedded systems (CRTES). However, manycores adoption by CRTES industry requires understanding task's timing behavior when their requests use manycore's network-on-chip (NoC) to access hardware shared resources. This paper analyzes the contention in wormhole-based NoC (wNoC) designs - widely implemented in the high-performance domain - for which we introduce a new metric: worst-contention delay (WCD) that captures wNoC impact on worst-case execution time (WCET) in a tighter manner than the existing metric, worst-case traversal time (WCTT). Moreover, we provide an analytical model of the WCD that requests can suffer in a wNoC and we validate it against wNoC designs resembling those in the Tilera-Gx36 and the Intel-SCC 48-core processors. Building on top of our WCD analytical model, we analyze the impact on WCD that different design parameters such as the number of virtual channels, and we make a set of recommendations on what wNoC setups to use in the context of CRTES.Peer ReviewedPostprint (author's final draft

Analysis and simulation of multiplexed single-bus networks with and without buffering

Performance issues of a single-bus interconnection network for multiprocessor systems, operating in a multiplexed way, are presented in this paper. Several models are developed and used to allow system performance evaluation. Comparisons with equivalent crossbar systems are provided. It is shown how crossbar EBW values can be reached and exceeded when appropriate operation parameters are chosen in a multiplexed single-bus system. Another architectural feature is considered, concerning the utilization of buffers at the memory modules. With the buffering scheme, memory interference can be reduced so that the system performance is practically improved.Peer ReviewedPostprint (published version

K-ary n-cube based off-chip communications architecture for high-speed packet processors

We present a detailed study of Higgs boson production in association with a single top quark at the LHC, at next-to-leading order accuracy in QCD. We consider total and differential cross sections, at the parton level as well as by matching short distance events to parton showers, for both t-channel and s-channel production. We provide predictions relevant for the LHC at 13 TeV together with a thorough evaluation of the residual uncertainties coming from scale variation, parton distributions, strong coupling constant and heavy quark masses. In addition, for t-channel production, we compare results as obtained in the 4-flavour and 5-flavour schemes, pinning down the most relevant differences between them. Finally, we study the sensitivity to a non-standard-model relative phase between the Higgs couplings to the top quark and to the weak bosons