Second-order neural core for bioinspired focal-plane dynamic image processing in CMOS

Based on studies of the mammalian retina, a bioinspired model for mixed-signal array processing has been implemented on silicon. This model mimics the way in which images are processed at the front-end of natural visual pathways, by means of programmable complex spatio-temporal dynamic. When embedded into a focal-plane processing chip, such a model allows for online parallel filtering of the captured image; the outcome of such processing can be used to develop control feedback actions to adapt the response of photoreceptors to local image features. Beyond simple resistive grid filtering, it is possible to program other spatio-temporal processing operators into the model core, such as nonlinear and anisotropic diffusion, among others. This paper presents analog and mixed-signal very large-scale integration building blocks to implement this model, and illustrates their operation through experimental results taken from a prototype chip fabricated in a 0.5-μm CMOS technology.European Union IST 2001 38097Ministerio de Ciencia y Tecnología TIC 2003 09817 C02 01Office of Naval Research (USA) N00014021088

NASA Thesaurus supplement: A four part cumulative supplement to the 1988 edition of the NASA Thesaurus (supplement 3)

The four-part cumulative supplement to the 1988 edition of the NASA Thesaurus includes the Hierarchical Listing (Part 1), Access Vocabulary (Part 2), Definitions (Part 3), and Changes (Part 4). The semiannual supplement gives complete hierarchies and accepted upper/lowercase forms for new terms

Design Of Neural Network Circuit Inside High Speed Camera Using Analog CMOS 0.35 ¼m Technology

Analog VLSI on-chip learning Neural Networks represent a mature technology for a large number of applications involving industrial as well as consumer appliances. This is particularly the case when low power consumption, small size and/or very high speed are required. This approach exploits the computational features of Neural Networks, the implementation efficiency of analog VLSI circuits and the adaptation capabilities of the on-chip learning feedback schema. High-speed video cameras are powerful tools for investigating for instance the biomechanics analysis or the movements of mechanical parts in manufacturing processes. In the past years, the use of CMOS sensors instead of CCDs has enabled the development of high-speed video cameras offering digital outputs , readout flexibility, and lower manufacturing costs. In this paper, we propose a high-speed smart camera based on a CMOS sensor with embedded Analog Neural Network

A 24-GHz, +14.5-dBm fully integrated power amplifier in 0.18-μm CMOS

A 24-GHz +14.5-dBm fully integrated power amplifier with on-chip 50-[ohm] input and output matching is demonstrated in 0.18-μm CMOS. The use of substrate-shielded coplanar waveguide structures for matching networks results in low passive loss and small die size. Simple circuit techniques based on stability criteria derived result in an unconditionally stable amplifier. The power amplifier achieves a power gain of 7 dB and a maximum single-ended output power of +14.5-dBm with a 3-dB bandwidth of 3.1 GHz, while drawing 100 mA from a 2.8-V supply. The chip area is 1.26 mm^2

MIDAS: Automated Approach to Design Microwave Integrated Inductors and Transformers on Silicon

The design of modern radiofrequency integrated circuits on silicon operating at microwave and millimeter-waves requires the integration of several spiral inductors and transformers that are not commonly available in the process design-kits of the technologies. In this work we present an auxiliary CAD tool for Microwave Inductor (and transformer) Design Automation on Silicon (MIDAS) that exploits commercial simulators and allows the implementation of an automatic design flow, including three-dimensional layout editing and electromagnetic simulations. In detail, MIDAS allows the designer to derive a preliminary sizing of the inductor (transformer) on the bases of the design entries (specifications). It draws the inductor (transformer) layers for the specific process design kit, including vias and underpasses, with or without patterned ground shield, and launches the electromagnetic simulations, achieving effective design automation with respect to the traditional design flow for RFICs. With the present software suite the complete design time is reduced significantly (typically 1 hour on a PC based on Intel® Pentium® Dual 1.80GHz CPU with 2-GB RAM). Afterwards both the device equivalent circuit and the layout are ready to be imported in the Cadence environment

A Fully Integrated 24-GHz Eight-Element Phased-Array Receiver in Silicon

This paper reports the first fully integrated 24-GHz eight-element phased-array receiver in a SiGe BiCMOS technology. The receiver utilizes a heterodyne topology and the signal combining is performed at an IF of 4.8 GHz. The phase-shifting with 4 bits of resolution is realized at the LO port of the first down-conversion mixer. A ring LC voltage-controlled oscillator (VCO) generates 16 different phases of the LO. An integrated 19.2-GHz frequency synthesizer locks the VCO frequency to a 75-MHz external reference. Each signal path achieves a gain of 43 dB, a noise figure of 7.4 dB, and an IIP3 of -11 dBm. The eight-path array achieves an array gain of 61 dB and a peak-to-null ratio of 20 dB and improves the signal-to-noise ratio at the output by 9 dB

Liquid cooling of non-uniform heat flux of chip circuit by submicrochannels

Sumbmicrochannels have been placed on the hotspots in a non-uniform heat generated chip circuit to increase the liquid/solid interaction area and then to enhance the heat dissipation. Main microchannels width is 185µm, which is twice the width of the submicrochannels and also includes the wall thickness of 35µm, and wall height is 500µm. The chip dimension is 10mm×10mm and the hotspot is 4mm×10m. Different positions of the hotspot have been investigated e.g. upstream, middle and downstream. Uniform heat flux is 100W/cm2 while for the hot spot is 150 W/cm2. Single channel simulation reveals that the downstream hotspot gives a lower temperature of the chip circuit surface; however the upstream hotspot has more uniform temperature distribution. A special design of manifold was adopted to ensure an equal mass distribution through the microchannels

State-of-the-art all-silicon sub-bandgap photodetectors at telecom and datacom wavelengths

Silicon-based technologies provide an ideal platform for the monolithic integration of photonics and microelectronics. In this context, a variety of passive and active silicon photonic devices have been developed to operate at telecom and datacom wavelengths, at which silicon has minimal optical absorption - due to its bandgap of 1.12 eV. Although in principle this transparency window limits the use of silicon for optical detection at wavelengths above 1.1 μm, in recent years tremendous advances have been made in the field of all-silicon sub-bandgap photodetectors at telecom and datacom wavelengths. By taking advantage of emerging materials and novel structures, these devices are becoming competitive with the more well-established technologies, and are opening new and intriguing perspectives. In this paper, a review of the state-of-the-art is presented. Devices based on defect-mediated absorption, two-photon absorption and the internal photoemission effect are reported, their working principles are elucidated and their performance discussed and compared