3,531 research outputs found

    Communication channel analysis and real time compressed sensing for high density neural recording devices

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    Next generation neural recording and Brain- Machine Interface (BMI) devices call for high density or distributed systems with more than 1000 recording sites. As the recording site density grows, the device generates data on the scale of several hundred megabits per second (Mbps). Transmitting such large amounts of data induces significant power consumption and heat dissipation for the implanted electronics. Facing these constraints, efficient on-chip compression techniques become essential to the reduction of implanted systems power consumption. This paper analyzes the communication channel constraints for high density neural recording devices. This paper then quantifies the improvement on communication channel using efficient on-chip compression methods. Finally, This paper describes a Compressed Sensing (CS) based system that can reduce the data rate by > 10x times while using power on the order of a few hundred nW per recording channel

    Physical Multi-Layer Phantoms for Intra-Body Communications

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    This paper presents approaches to creating tissue mimicking materials that can be used as phantoms for evaluating the performance of Body Area Networks (BAN). The main goal of the paper is to describe a methodology to create a repeatable experimental BAN platform that can be customized depending on the BAN scenario under test. Comparisons between different material compositions and percentages are shown, along with the resulting electrical properties of each mixture over the frequency range of interest for intra-body communications; 100 KHz to 100 MHz. Test results on a composite multi-layer sample are presented confirming the efficacy of the proposed methodology. To date, this is the first paper that provides guidance on how to decide on concentration levels of ingredients, depending on the exact frequency range of operation, and the desired matched electrical characteristics (conductivity vs. permittivity), to create multi-layer phantoms for intra-body communication applications

    Guest Editorial—Special Issue on Selected Papers From ISCAS 2009

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    A Wireless Power Transfer System for Biomedical Implants based on an isolated Class-E DC-DC Converter with Power Regulation Capability

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    In this paper, the design of a wireless power transfer system (WPT) targeting biomedical implants is considered. The novelty of the approach is to propose a co-design of the transmitter and receiver side based on the design of class-E isolated DC-DC converters. The solution, along with the simple introduction of a shunt regulator at the receiver, allows us to solve the problem of ensuring optimal efficiency in the WPT link. In conventional solutions, in order to cope with coupling factor and load variations, information from the receiver is needed, which is usually relayed back onto the transmitter by means of telemetry. With the proposed approach, a very simple minimum power point tracking (mPPT) algorithm can be used to maximize the WPT efficiency based on the information already available at the transmitter side. This reduces the complexity of the circuitry of the implant and thereby its power overhead and possibly its size, both being crucial constraints of a biomedical implant

    PIN generation using EEG : a stability study

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    In a previous study, it has been shown that brain activity, i.e. electroencephalogram (EEG) signals, can be used to generate personal identification number (PIN). The method was based on brain–computer interface (BCI) technology using a P300-based BCI approach and showed that a single-channel EEG was sufficient to generate PIN without any error for three subjects. The advantage of this method is obviously its better fraud resistance compared to conventional methods of PIN generation such as entering the numbers using a keypad. Here, we investigate the stability of these EEG signals when used with a neural network classifier, i.e. to investigate the changes in the performance of the method over time. Our results, based on recording conducted over a period of three months, indicate that a single channel is no longer sufficient and a multiple electrode configuration is necessary to maintain acceptable performances. Alternatively, a recording session to retrain the neural network classifier can be conducted on shorter intervals, though practically this might not be viable

    Applications of Graphene at Microwave Frequencies

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    In view to the epochal scenarios that nanotechnology discloses, nano-electronics has the potential to introduce a paradigm shift in electronic systems design similar to that of the transition from vacuum tubes to semiconductor devices. Since low dimensional (1D and 2D) nano-structured materials exhibit unprecedented electro-mechanical properties in a wide frequency range, including radio-frequencies (RF), microwave nano-electronics provides an enormous and yet widely undiscovered opportunity for the engineering community. Carbon nano-electronics is one of the main research routes of RF/microwave nano-electronics. In particular, graphene has shown proven results as an emblematic protagonist, and a real solution for a wide variety of microwave electronic devices and circuits. This paper introduces graphene properties in the microwave range, and presents a paradigm of novel graphene-based devices and applications in the microwave/RF frequency range

    Inverter-Based Low-Voltage CCII- Design and Its Filter Application

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    This paper presents a negative type second-generation current conveyor (CCII-). It is based on an inverter-based low-voltage error amplifier, and a negative current mirror. The CCII- could be operated in a very low supply voltage such as ±0.5V. The proposed CCII- has wide input voltage range (±0.24V), wide output voltage (±0.24V) and wide output current range (±24mA). The proposed CCII- has no on-chip capacitors, so it can be designed with standard CMOS digital processes. Moreover, the architecture of the proposed circuit without cascoded MOSFET transistors is easily designed and suitable for low-voltage operation. The proposed CCII- has been fabricated in TSMC 0.18Όm CMOS processes and it occupies 1189.91 x 1178.43Όm2 (include PADs). It can also be validated by low voltage CCII filters
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