Late allocation and early release of physical registers

The register file is one of the critical components of current processors in terms of access time and power consumption. Among other things, the potential to exploit instruction-level parallelism is closely related to the size and number of ports of the register file. In conventional register renaming schemes, both register allocation and releasing are conservatively done, the former at the rename stage, before registers are loaded with values, and the latter at the commit stage of the instruction redefining the same register, once registers are not used any more. We introduce VP-LAER, a renaming scheme that allocates registers later and releases them earlier than conventional schemes. Specifically, physical registers are allocated at the end of the execution stage and released as soon as the processor realizes that there will be no further use of them. VP-LAER enhances register utilization, that is, the fraction of allocated registers having a value to be read in the future. Detailed cycle-level simulations show either a significant speedup for a given register file size or a reduction in the register file size for a given performance level, especially for floating-point codes, where the register file pressure is usually high.Peer ReviewedPostprint (published version

The Global sphere reconstruction (GSR) - Demonstrating an independent implementation of the astrometric core solution for Gaia

Context. The Gaia ESA mission will estimate the astrometric and physical data of more than one billion objects, providing the largest and most precise catalog of absolute astrometry in the history of Astronomy. The core of this process, the so-called global sphere reconstruction, is represented by the reduction of a subset of these objects which will be used to define the celestial reference frame. As the Hipparcos mission showed, and as is inherent to all kinds of absolute measurements, possible errors in the data reduction can hardly be identified from the catalog, thus potentially introducing systematic errors in all derived work. Aims. Following up on the lessons learned from Hipparcos, our aim is thus to develop an independent sphere reconstruction method that contributes to guarantee the quality of the astrometric results without fully reproducing the main processing chain. Methods. Indeed, given the unfeasibility of a complete replica of the data reduction pipeline, an astrometric verification unit (AVU) was instituted by the Gaia Data Processing and Analysis Consortium (DPAC). One of its jobs is to implement and operate an independent global sphere reconstruction (GSR), parallel to the baseline one (AGIS, namely Astrometric Global Iterative Solution) but limited to the primary stars and for validation purposes, to compare the two results, and to report on any significant differences. Results. Tests performed on simulated data show that GSR is able to reproduce at the sub-$\mu$as level the results of the AGIS demonstration run presented in Lindegren et al. (2012). Conclusions. Further development is ongoing to improve on the treatment of real data and on the software modules that compare the AGIS and GSR solutions to identify possible discrepancies above the tolerance level set by the accuracy of the Gaia catalog.Comment: Accepted for publication on Astronomy & Astrophysic

The first WASP public data release

The WASP (wide angle search for planets) project is an exoplanet transit survey that has been automatically taking wide field images since 2004. Two instruments, one in La Palma and the other in South Africa, continually monitor the night sky, building up light curves of millions of unique objects. These light curves are used to search for the characteristics of exoplanetary transits. This first public data release (DR1) of the WASP archive makes available all the light curve data and images from 2004 up to 2008 in both the Northern and Southern hemispheres. A web interface () to the data allows easy access over the Internet. The data set contains 3 631 972 raw images and 17 970 937 light curves. In total the light curves have 119 930 299 362 data points available between them

Reducing branch delay to zero in pipelined processors

A mechanism to reduce the cost of branches in pipelined processors is described and evaluated. It is based on the use of multiple prefetch, early computation of the target address, delayed branch, and parallel execution of branches. The implementation of this mechanism using a branch target instruction memory is described. An analytical model of the performance of this implementation makes it possible to measure the efficiency of the mechanism with a very low computational cost. The model is used to determine the size of cache lines that maximizes the processor performance, to compare the performance of the mechanism with that of other schemes, and to analyze the performance of the mechanism with two alternative cache organizations.Peer ReviewedPostprint (published version