Management considerations of massive hemoptysis while on extracorporeal membrane oxygenation.

BACKGROUND: Veno-arterial extracorporeal membrane oxygenation (V-A ECMO) is a life-saving procedure in patients with both respiratory and cardiac failure. Bleeding complications are common since patients must be maintained on anticoagulation. Massive hemoptysis is a rare complication of ECMO; however, it may result in death if not managed thoughtfully and expeditiously. METHODS: A retrospective chart review was performed of consecutive ECMO patients from 7/2010-8/2014 to identify episodes of massive hemoptysis. The management of and the outcomes in these patients were studied. Massive hemoptysis was defined as an inability to control bleeding (\u3e300 mL/day) from the endotracheal tube with conventional maneuvers, such as bronchoscopy with cold saline lavage, diluted epinephrine lavage and selective lung isolation. All of these episodes necessitated disconnecting the ventilator tubing and clamping the endotracheal tube, causing full airway tamponade. RESULTS: During the period of review, we identified 118 patients on ECMO and 3 (2.5%) patients had the complication of massive hemoptysis. One case was directly related to pulmonary catheter migration and the other two were spontaneous bleeding events that were propagated by antiplatelet agents. All three patients underwent bronchial artery embolization in the interventional radiology suite. Anticoagulation was held during the period of massive hemoptysis without any embolic complications. There was no recurrent bleed after appropriate intervention. All three patients were successfully separated from ECMO. CONCLUSIONS: Bleeding complications remain a major issue in patients on ECMO. Disconnection of the ventilator and clamping the endotracheal tube with full respiratory and cardiac support by V-A ECMO is safe. Early involvement of interventional radiology to embolize any potential sources of the bleed can prevent re-hemoptysis and enable continued cardiac and respiratory recovery

The Advocate

Crowley Named Winner of 1977 Keefe Award; Alumni Secretary Blake Named to Head Placement; McLaughlin Announced Faculty Appointments; Graduation Planned for Damrosch Parkhttps://ir.lawnet.fordham.edu/student_the_advocate/1072/thumbnail.jp

Migrated Avalon Veno-Venous Extracorporeal Membrane Oxygenation Cannula: How to Adjust Without Interruption of Flow.

The Avalon dual lumen cannula is presently the cannula of choice for veno-venous extracorporeal membrane oxygenation (VV-ECMO) via right internal jugular cannulation. This cannula establishes VV-ECMO with a single cannulation; however, it requires appropriate positioning to gain adequate oxygenation. Malposition of this cannula can cause inadequate ECMO flow, hypoxia, and structural injury. We have experienced two cases of migration: one into the hepatic vein and the other into the right ventricle. The former was repositioned using echocardiographic guidance without using a guidewire. The latter was repositioned using a guidewire from the femoral vein under fluoroscopy, without antegrade wire placement into the Avalon cannula, discontinuation of ECMO, or bleeding

On the suitability and development of layout templates for analog layout reuse and layout-aware synthesis

Accelerating the synthesis of increasingly complex analog integrated circuits is key to bridge the widening gap between what we can integrate and what we can design while meeting ever-tightening time-to-market constraints. It is a well-known fact in the semiconductor industry that such goal can only be attained by means of adequate CAD methodologies, techniques, and accompanying tools. This is particularly important in analog physical synthesis (a.k.a. layout generation), where large sensitivities of the circuit performances to the many subtle details of layout implementation (device matching, loading and coupling effects, reliability, and area features are of utmost importance to analog designers), render complete automation a truly challenging task. To approach the problem, two directions have been traditionally considered, knowledge-based and optimization-based, both with their own pros and cons. Besides, recently reported solutions oriented to speed up the overall design flow by means of reuse-based practices or by cutting off time-consuming, error-prone spins between electrical and layout synthesis (a technique known as layout-aware synthesis), rely on a outstandingly rapid yet efficient layout generation method. This paper analyses the suitability of procedural layout generation based on templates (a knowledge-based approach) by examining the requirements that both layout reuse and layout-aware solutions impose, and how layout templates face them. The ability to capture the know-how of experienced layout designers and the turnaround times for layout instancing are considered main comparative aspects in relation to other layout generation approaches. A discussion on the benefit-cost trade-off of using layout templates is also included. In addition to this analysis, the paper delves deeper into systematic techniques to develop fully reusable layout templates for analog circuits, either for a change of the circuit sizing (i.e., layout retargeting) or a change of the fabrication process (i.e., layout migration). Several examples implemented with the Cadence's Virtuoso tool suite are provided as demonstration of the paper's contributions.Ministerio de Educación y Ciencia TEC2004-0175

Randomised positive control trial of NSAID and antimicrobial treatment for calf fever caused by pneumonia

One hundred and fifty-four preweaning calves were followed between May and October 2015. Calves were fitted with continuous monitoring temperature probes (TempVerified FeverTag), programmed so a flashing light emitting diode (LED) light was triggered following six hours of a sustained ear canal temperature of ≥39.7°C. A total of 83 calves (61.9 per cent) developed undifferentiated fever, with a presumptive diagnosis of pneumonia through exclusion of other calf diseases. Once fever was detected, calves were randomly allocated to treatment groups. Calves in group 1 (NSAID) received 2 mg/kg flunixin meglumine (Allevinix, Merial) for three consecutive days and group 2 (antimicrobial) received 6 mg/kg gamithromycin (Zactran, Merial). If fever persisted for 72 hours after the initial treatment, calves were given further treatment (group 1 received antimicrobial and group 2 received NSAID). Calves in group 1 (NSAID) were five times more likely (P=0.002) to require a second treatment (the antimicrobial) after 72 hours to resolve the fever compared with the need to give group 2 (antimicrobial) calves a second treatment (NSAID). This demonstrates the importance of ongoing monitoring and follow-up of calves with respiratory disease. However, of calves with fever in group 1 (NSAID), 25.7 per cent showed resolution following NSAID-only treatment with no detrimental effect on the development of repeated fever or daily live weight gain. This suggests that NSAID alone may be a useful first-line treatment, provided adequate attention is given to ongoing monitoring to identify those cases that require additional antimicrobial treatment

Automatic synthesis of analog layout : a survey

A review of recent research in the automatic synthesis of physical geometry for analog integrated circuits is presented. On introduction, an explanation of the difficulties involved in analog layout as opposed to digital layout is covered. Review of the literature then follows. Emphasis is placed on the exposition of general methods for addressing problems specific to analog layout, with the details of specific systems only being given when they surve to illustrate these methods well. The conclusion discusses problems remaining and offers a prediction as to how technology will evolve to solve them. It is argued that although progress has been and will continue to be made in the automation of analog IC layout, due to fundamental differences in the nature of analog IC design as opposed to digital design, it should not be expected that the level of automation of the former will reach that of the latter any time soon

Geometrically-constrained, parasitic-aware synthesis of analog ICs

In order to speed up the design process of analog ICs, iterations between different design stages should be avoided as much as possible. More specifically, spins between electrical and physical synthesis should be reduced for this is a very time-consuming task: if circuit performance including layout-induced degradations proves unacceptable, a re-design cycle must be entered, and electrical, physical, or both synthesis processes, would have to be repeated. It is also worth noting that if geometric optimization (e.g., area minimization) is undertaken after electrical synthesis, it may add up as another source of unexpected degradation of the circuit performance due to the impact of the geometric variables (e.g., transistor folds) on the device and the routing parasitic values. This awkward scenario is caused by the complete separation of said electrical and physical synthesis, a design practice commonly followed so far. Parasitic-aware synthesis, consisting in including parasitic estimates to the circuit netlist directly during electrical synthesis, has been proposed as solution. While most of the reported contributions either tackle parasitic-aware synthesis without paying special attention to geometric optimization or approach both issues only partially, this paper addresses the problem in a unified way. In what has been called layout-aware electrical synthesis, a simulation-based optimization algorithm explores the design space with geometric variables constrained to meet certain user-defined goals, which provides reliable estimates of layout-induced parasitics at each iteration, and, thereby, accurate evaluation of the circuit ultimate performance. This technique, demonstrated here through several design examples, requires knowing layout details beforehand; to facilitate this, procedural layout generation is used as physical synthesis approach due to its rapidness and ability to capture analog layout know-how.Ministerio de Educación y Ciencia TEC2004-0175