Automating the IEEE std. 1500 compliance verification for embedded cores

The IEEE 1500 standard for embedded core testing proposes a very effective solution for testing modern system-on-chip (SoC). It proposes a flexible hardware test wrapper architecture, together with a core test language (CTL) used to describe the implemented wrapper functionalities. Already several IP providers have announced compliance in both existing and future design blocks. In this paper we address the challenge of guaranteeing the compliance of a wrapper architecture and its CTL description to the IEEE std. 1500. This is a mandatory step to fully trust the wrapper functionalities in applying the test sequences to the core. The proposed solution aims at implementing a verification framework allowing core providers and/or integrators to automatically verify the compliancy of their products (sold or purchased) to the standar

Enhanced P1500 Compliant Wrapper Suitable for Delay-Fault Testing of Embedded Cores

Continual advances in the manufacturing processes of integrated circuits provide designers the ability to create more complex and denser architectures and increased functionality on a single chip. The increased usage of embedded cores necessitates a core-based test strategy in which cores are also tested separately. The IEEE P1500 proposed standard for embedded core test (SECT) is a standard under development which aims is to improve the testing of core-based system chips. This paper deals with the enhancement of the test wrapper and wrapper cells to provide a structure to be able to test embedded cores for delay faults. This approach allows delay fault testing of cores by using the digital oscillation test method and the help of the enhanced elements while staying compliant to the P1500 standard