Study Of Esd Effects On Rf Power Amplifiers

Today, ESD is a major consideration in the design and manufacture of ICs. ESD problems are increasing in the electronics industry because of the increasing trend toward higher speed and smaller device sizes. There is growing interest in knowing the effects of ESD protection circuit on the performance of semiconductor integrated circuits (ICs) because of the impact it has on core RF circuit performance. This study investigated the impact of ESD protection circuit on RF Power amplifiers. Even though ESD protection for digital circuits has been known for a while, RF-ESD is a challenge. From a thorough literature search on prior art ESD protection circuits, Silicon controlled rectifier was found to be most effective and reliable ESD protection for power amplifier circuit. A SCR based ESD protection was used to protect the power amplifier and a model was developed to gain better understanding of ESD protected power amplifiers. Simulated results were compared and contrasted against theoretically derived equations. A 5.2GHz fully ESD protected Class AB power amplifier was designed and simulated using TSMC 0.18 um technology. Further, the ESD protection circuit was added to a cascoded Class-E power amplifier operating at 5.2 GHz. ADS simulation results were used to analyze the PA’s RF performance degradation. Various optimization techniques were used to improve the RF circuit performance

Design, Characterization and Analysis of Component Level Electrostatic Discharge (ESD) Protection Solutions

Electrostatic Discharges (ESD) is a significant hazard to electronic components and systems. Based on a specific process technology, a given circuit application requires a customized ESD consideration that meets all the requirements such as the core circuit\u27s operating condition, maximum accepted leakage current, breakdown conditions for the process and overall device sizes. In every several years, there will be a new process technology becomes mature, and most of those new technology requires custom design of effective ESD protection solution. And usually the design window will shrinks due to the evolving of the technology becomes smaller and smaller. The ESD related failure is a major IC reliability concern and results in a loss of millions dollars each year in the semiconductor industry. To emulate the real word stress condition, several ESD stress models and test methods have been developed. The basic ESD models are Human Body model (HBM), Machine Mode (MM), and Charge Device Model (CDM). For the system-level ESD robustness, it is defined by different standards and specifications than component-level ESD requirements. International Electrotechnical Commission (IEC) 61000-4-2 has been used for the product and the Human Metal Model (HMM) has been used for the system at the wafer level. Increasingly stringent design specifications are forcing original equipment manufacturers (OEMs) to minimize the number of off-chip components. This is the case in emerging multifunction mobile, industrial, automotive and healthcare applications. It requires a high level of ESD robustness and the integrated circuit (IC) level, while finding ways to streamline the ESD characterization during early development cycle. To enable predicting the ESD performance of IC\u27s pins that are directly exposed to a system-level stress condition, a new the human metal model (HMM) test model has been introduced. In this work, a new testing methodology for product-level HMM characterization is introduced. This testing framework allows for consistently identifying ESD-induced failures in a product, substantially simplifying the testing process, and significantly reducing the product evaluation time during development cycle. It helps eliminates the potential inaccuracy provided by the conventional characterization methodology. For verification purposes, this method has been applied to detect the failures of two different products. Addition to the exploration of new characterization methodology that provides better accuracy, we also have looked into the protection devices itself. ICs for emerging high performance precision data acquisition and transceivers in industrial, automotive and wireless infrastructure applications require effective and ESD protection solutions. These circuits, with relatively high operating voltages at the Input/Output (I/O) pins, are increasingly being designed in low voltage Complementary Metal-Oxide-Semiconductor (CMOS) technologies to meet the requirements of low cost and large scale integration. A new dual-polarity SCR optimized for high bidirectional blocking voltages, high trigger current and low capacitance is realized in a sub 3-V, 180-nm CMOS process. This ESD device is designed for a specific application where the operating voltage at the I/O is larger than that of the core circuit. For instance, protecting high voltage swing I/Os in CMOS data acquisition system (DAS) applications. In this reference application, an array of thin film resistors voltage divider is directly connected to the interface pin, reducing the maximum voltage that is obtained at the core device input down to ± 1-5 V. Its ESD characteristics, including the trigger voltage and failure current, are compared against those of a typical CMOS-based SCR. Then, we have looked into the ESD protection designs into more advanced technology, the 28-nm CMOS. An ESD protection design builds on the multiple discharge-paths ESD cell concept and focuses the attention on the detailed design, optimization and realization of the in-situ ESD protection cell for IO pins with variable operation voltages. By introducing different device configurations fabricated in a 28-nm CMOS process, a greater flexibility in the design options and design trade-offs can be obtained in the proposed topology, thus achieving a higher integration and smaller cell size definition for multi-voltage compatibility interface ESD protection applications. This device is optimized for low capacitance and synthesized with the circuit IO components for in-situ ESD protection in communication interface applications developed in a 28-nm, high-k, and metal-gate CMOS technology. ESD devices have been used in different types of applications and also at different environment conditions, such as high temperature. At the last section of this research work, we have performed an investigation of several different ESD devices\u27 performance under various temperature conditions. And it has been shown that the variations of the device structure can results different ESD performance, and some devices can be used at the high temperature and some cannot. And this investigation also brings up a potential threat to the current ESD protection devices that they might be very vulnerable to the latch-up issue at the higher temperature range

Understanding, modeling, and mitigating system-level ESD in integrated circuits

This dissertation describes several studies regarding the effects of system-level electrostatic discharge (ESD) and how to model and mitigate them. The topics in this dissertation fall into two broad categories: modeling pieces of a system-level ESD test setup and phenomenological studies. Simulation is an important tool for achieving quality designs quickly. However, modeling methodologies for system-level ESD are not yet mature. This dissertation aims to improve (i) simulation models of ESD protection elements, (ii) simulation models of ESD guns, and (iii) analytic models of rail-clamp circuits used for power-on ESD protection. Simulation models for two common ESD protection elements, diodes and silicon controlled rectifiers (SCR) are presented and evaluated, specifically with regard to the origins of poor voltage clamping. These models can be used for ESD network design and simulation; their applicability is not limited only to system-level ESD. Next, a circuit simulation model for an ESD gun (used to produce system-level ESD stresses) is presented. This model can be used for trouble-shooting and design. Lastly, an analytic model of rail-clamp circuits during system-level ESD is presented. These circuits can produce unstable oscillations or ringing on the supply; such problems must be eliminated during design. Analytic models help the designer understand how circuit parameters will impact the circuit’s performance. System-level ESD is a relatively new requirement being imposed on IC manufacturers; as such, current understanding of how system-level ESD affects ICs is not yet mature. This dissertation includes two studies that expand upon this knowledge. The first demonstrates that ground bounce due system-level ESD stress can lead to severe problems, including latch-up and power integrity problems. The second reports observations regarding input noise signals at an IC pin during system-level ESD stress. Lastly, this dissertation discusses experimental design of a test chip that will be manufactured shortly after this dissertation is completed. These experiments focus on observing and suppressing various errors that can occur during system-level ESD, arising from both noise at the inputs and power fluctuations. Additionally, this test chip includes standalone test structures that are used to reproduce power supply problems predicted in other sections of this dissertation

Survey on individual components for a 5 GHz receiver system using 130 nm CMOS technology

La intención de esta tesis es recopilar información desde un punto de vista general sobre los diferentes tipos de componentes utilizados en un receptor de señales a 5 GHz utilizando tecnología CMOS. Se ha realizado una descripción y análisis de cada uno de los componentes que forman el sistema, destacando diferentes tipos de configuraciones, figuras de mérito y otros parámetros. Se muestra una tabla resumen al final de cada sección, comparando algunos diseños que se han ido presentando a lo largo de los años en conferencias internacionales de la IEEE.The intention of this thesis is to gather information from an overview point about the different types of components used in a 5 GHz receiver using CMOS technology. A review of each of the components that form the system has been made, highlighting different types of configurations, figure of merits and parameters. A summary table is shown at the end of each section, comparing many designs that have been presented over the years at international conferences of the IEEE.Departamento de Ingeniería Energética y FluidomecánicaGrado en Ingeniería en Electrónica Industrial y Automátic

CMOS RF low noise amplifier with high ESD immunity.

Tang Siu Kei.Thesis (M.Phil.)--Chinese University of Hong Kong, 2004.Includes bibliographical references (leaves 107-111).Abstracts in English and Chinese.Acknowledgements --- p.iiAbstract --- p.iiiList of Figures --- p.xiList of Tables --- p.xviChapter Chapter 1 --- Introduction --- p.1Chapter 1.1 --- Overview of Electrostatic Discharge --- p.1Chapter 1.1.1 --- Classification of Electrostatic Discharge Models --- p.1Chapter 1.2 --- Electrostatic Discharge in CMOS RF Circuits --- p.4Chapter 1.3 --- Research Goal and Contribution --- p.6Chapter 1.4 --- Thesis Outline --- p.6Chapter Chapter 2 --- Performance Parameters of Amplifier --- p.8Chapter 2.1 --- Amplifier Gain --- p.8Chapter 2.2 --- Noise Factor --- p.9Chapter 2.3 --- Linearity --- p.11Chapter 2.3.1 --- 1-dB Compression Point --- p.13Chapter 2.3.2 --- Third-Order Intercept Point --- p.14Chapter 2.4 --- Return Loss --- p.16Chapter 2.5 --- Power Consumption --- p.18Chapter 2.6 --- HBM ESD Withstand Voltage --- p.19Chapter Chapter 3 --- ESD Protection Methodology for Low Noise Amplifier --- p.21Chapter 3.1 --- Dual-Diode Circuitry --- p.22Chapter 3.1.1 --- Working Principle --- p.22Chapter 3.1.2 --- Drawbacks --- p.24Chapter 3.2 --- Shunt-Inductor Method --- p.25Chapter 3.2.1 --- Working Principle --- p.25Chapter 3.2.2 --- Drawbacks --- p.27Chapter 3.3 --- Common-Gate Input Stage Method --- p.28Chapter 3.3.1 --- Built-in ESD Protecting Mechanism --- p.29Chapter 3.3.2 --- Competitiveness --- p.31Chapter Chapter 4 --- Design Theory of Low Noise Amplifier --- p.32Chapter 4.1 --- Small-Signal Modeling --- p.33Chapter 4.2 --- Method of Input Termination --- p.33Chapter 4.2.1 --- Resistive Termination --- p.34Chapter 4.2.2 --- Shunt-Series Feedback --- p.34Chapter 4.2.3 --- l/gm Termination --- p.35Chapter 4.2.4 --- Inductive Source Degeneration --- p.36Chapter 4.3 --- Method of Gain Enhancement --- p.38Chapter 4.3.1 --- Tuned Amplifier --- p.38Chapter 4.3.2 --- Multistage Amplifier --- p.40Chapter 4.4 --- Improvement of Reverse Isolation --- p.41Chapter 4.4.1 --- Common-Gate Amplifier --- p.41Chapter 4.4.2 --- Cascoded Amplifier --- p.42Chapter Chapter 5 --- Noise Analysis of Low Noise Amplifier --- p.44Chapter 5.1 --- Noise Sources of MOS Transistor --- p.44Chapter 5.2 --- Noise Calculation using Noisy Two-Port Network --- p.46Chapter 5.3 --- Noise Calculation using Small-Signal Model --- p.49Chapter 5.3.1 --- Low Noise Amplifier with Inductive Source Degeneration --- p.49Chapter 5.3.2 --- Common-Gate Low Noise Amplifier --- p.52Chapter Chapter 6 --- Design of an ESD-protected CMOS Low Noise Amplifier --- p.54Chapter 6.1 --- Design of DC Biasing Circuitry --- p.55Chapter 6.2 --- Design of Two-Stage Architecture --- p.57Chapter 8.3.1 --- Design of Common-Gate Input Stage --- p.57Chapter 8.3.2 --- Design of Second-Stage Amplifier --- p.59Chapter 6.3 --- Stability Consideration --- p.61Chapter 6.4 --- Design of Matching Networks --- p.62Chapter 6.4.1 --- Design of Inter-Stage Matching Network --- p.64Chapter 6.4.2 --- Design of Input and Output Matching Networks --- p.67Chapter Chapter 7 --- Layout Considerations --- p.70Chapter 7.1 --- MOS Transistor --- p.70Chapter 7.2 --- Capacitor --- p.72Chapter 7.3 --- Spiral Inductor --- p.74Chapter 7.4 --- Layout of the Proposed Low Noise Amplifier --- p.76Chapter 7.5 --- Layout of the Common-Source Low Noise Amplifier --- p.79Chapter 7.6 --- Comparison between Schematic and Post-Layout Simulation Results --- p.81Chapter Chapter 8 --- Measurement Results --- p.82Chapter 8.1 --- Experimental Setup --- p.82Chapter 8.1.1 --- Testing Circuit Board --- p.83Chapter 8.1.2 --- Experimental Setup for s-parameter --- p.84Chapter 8.1.3 --- Experimental Setup for Noise Figure --- p.84Chapter 8.1.4 --- Experimental Setup for 1-dB Compression Point --- p.85Chapter 8.1.5 --- Experimental Setup for Third-Order Intercept Point --- p.86Chapter 8.1.6 --- Setup for HBM ESD Test --- p.87Chapter 8.2 --- Measurement Results of the Proposed Low Noise Amplifier --- p.89Chapter 8.2.1 --- S-parameter Measurement --- p.90Chapter 8.2.2 --- Noise Figure Measurement --- p.91Chapter 8.2.3 --- Measurement of 1-dB Compression Point --- p.92Chapter 8.2.4 --- Measurement of Third-Order Intercept Point --- p.93Chapter 8.2.5 --- HBM ESD Test --- p.94Chapter 8.2.6 --- Summary of Measurement Results --- p.95Chapter 8.3 --- Measurement Results of the Common-Source Low Noise Amplifier --- p.96Chapter 8.3.1 --- s-parameter Measurement --- p.97Chapter 8.3.2 --- Noise Figure Measurement --- p.98Chapter 8.3.3 --- Measurement of 1-dB Compression Point --- p.99Chapter 8.3.4 --- Measurement of Third-Order Intercept Point --- p.100Chapter 8.3.5 --- HBM ESD Test --- p.101Chapter 8.3.6 --- Summary of Measurement Results --- p.102Chapter 8.4 --- Performance Comparison between Different Low Noise Amplifier Designs --- p.103Chapter Chapter 9 --- Conclusion and Future Work --- p.105Chapter 9.1 --- Conclusion --- p.105Chapter 9.2 --- Future Work --- p.106References --- p.107Author's Publications --- p.11

Microwave CMOS VCOs and Front-Ends - using integrated passives on-chip and on-carrier

The increasing demand for high data rates in wireless communication systems is increasing the requirements on the transceiver front-ends, as they are pushed to utilize more and wider bands at higher frequencies. The work in this thesis is focused on receiver front-ends composed of Low Noise Amplifiers (LNAs), Mixers, and Voltage Controlled Oscillators (VCOs) operating at microwave frequencies. Traditionally, microwave electronics has used exclusive and more expensive semiconductor technologies (III-V materials). However, the rapid development of consumer electronics (e.g. video game consoles) the last decade has pushed the silicon CMOS IC technology towards even smaller feature sizes. This has resulted in high speed transistors (high fT and fmax) with low noise figures. However, as the breakdown voltages have decreased, a lower supply voltage must be used, which has had a negative impact on linearity and dynamic range. Nonetheless, todays downscaled CMOS technology is a feasible alternative for many microwave and even millimeter wave applications. The low quality factor (Q) of passive components on-chip usually limits the high frequency performance. For inductors realized in a standard CMOS process the substrate coupling results in a degraded Q. The quality factor can, however, be improved by moving the passive components off-chip and integrating them on a low loss carrier. This thesis therefore features microwave front-end and VCO designs in CMOS, where some designs have been flip-chip mounted on carriers featuring high Q inductors and low loss baluns. The thesis starts with an introduction to wireless communication, receiver architectures, front-end receiver blocks, and low loss carrier technology, followed by the included papers. The six included papers show the capability of CMOS and carrier technology at microwave frequencies: Papers II, III, and VI demonstrate fully integrated CMOS circuit designs. An LC-VCO using an accumulation mode varactor is presented in Paper II, a QVCO using 4-bit switched tuning is shown in Paper III, and a quadrature receiver front-end (including QVCO) is demonstrated in paper VI. Papers I and IV demonstrate receiver front-ends using low loss baluns on carrier for the LO and RF signals. Paper IV also includes a front-end using single-ended RF input which is converted to differential form in a novel merged LNA and balun. A VCO demonstrating the benefits of a high Q inductor on carrier is presented in Paper V

Advances in Solid State Circuit Technologies

This book brings together contributions from experts in the fields to describe the current status of important topics in solid-state circuit technologies. It consists of 20 chapters which are grouped under the following categories: general information, circuits and devices, materials, and characterization techniques. These chapters have been written by renowned experts in the respective fields making this book valuable to the integrated circuits and materials science communities. It is intended for a diverse readership including electrical engineers and material scientists in the industry and academic institutions. Readers will be able to familiarize themselves with the latest technologies in the various fields

Design of reliable and energy-efficient high-speed interface circuits

The data-rate demand in high-speed interface circuits increases exponentially every year. High-speed I/Os are better implemented in advanced process technologies for lower-power systems, with the advantages of improved driving capability of the transistors and reduced parasitic capacitance. However, advanced technologies are not necessarily advantageous in terms of device reliability; in particular device failure from electrostatic discharge (ESD) becomes more likely in nano-scale process nodes. In order to secure ESD resiliency, the size of ESD devices on I/O pads should be sufficiently large, which may potentially reduce I/O speed. These two conflicting requirements in high-speed I/O design sometimes require sacrifice to one of the two properties. In this dissertation, three different approaches are proposed to achieve reliable and energy-efficient interface circuits. As the first approach, a novel ESD self-protection scheme to utilize “adaptive active bias conditioning” is proposed to reduce voltage stress on the vulnerable transistors, thereby reducing the burden on ESD protection devices. The second approach is to cancel out effective parasitic capacitance from ESD devices by the T-coil network. Voltage overshoot generated by magnetic coupling of the T-coil network can be suppressed by the proposed “inductance halving” technique, which reduces mutual inductance during ESD. The last approach employs system-level knowledge in the design of an ADC-based receiver for high intersymbol interference (ISI) channels. As a system-level performance metric, bit-error rate (BER) is adopted to mitigate a bit-resolution requirement in “BER-optimal ADC”, which can lead to 2× power-efficiency in the flash ADC and achieve a better BER performance

Analog-Digital System Modeling for Electromagnetic Susceptibility Prediction

The thesis is focused on the noise susceptibility of communication networks. These analog-mixed signal systems operate in an electrically noisy environment, in presence of multiple equipments connected by means of long wiring. Every module communicates using a transceiver as an interface between the local digital signaling and the data transmission through the network. Hence, the performance of the IC transceiver when affected by disturbances is one of the main factors that guarantees the EM immunity of the whole equipment. The susceptibility to RF and transient disturbances is addressed at component level on a CAN transceiver as a test case, highlighting the IC features critical for noise immunity. A novel procedure is proposed for the IC modeling for mixed-signal immunity simulations of communication networks. The procedure is based on a gray-box approach, modeling IC ports with a physical circuit and the internal links with a behavioural block. The parameters are estimated from time and frequency domain measurements, allowing accurate and efficient reproduction of non-linear device switching behaviours. The effectiveness of the modeling process is verified by applying the proposed technique to a CAN transceiver, involved in a real immunity test on a data communication link. The obtained model is successfully implemented in a commercial solver to predict both the functional signals and the RF noise immunity at component level. The noise immunity at system level is then evaluated on a complete communication network, analyzing the results of several tests on a realistic CAN bus. After developing models for wires and injection probes, a noise immunity test in avionic environment is carried out in a simulation environment, observing good overall accuracy and efficiency