Design, Characterization and Analysis of Component Level Electrostatic Discharge (ESD) Protection Solutions

Electrostatic Discharges (ESD) is a significant hazard to electronic components and systems. Based on a specific process technology, a given circuit application requires a customized ESD consideration that meets all the requirements such as the core circuit\u27s operating condition, maximum accepted leakage current, breakdown conditions for the process and overall device sizes. In every several years, there will be a new process technology becomes mature, and most of those new technology requires custom design of effective ESD protection solution. And usually the design window will shrinks due to the evolving of the technology becomes smaller and smaller. The ESD related failure is a major IC reliability concern and results in a loss of millions dollars each year in the semiconductor industry. To emulate the real word stress condition, several ESD stress models and test methods have been developed. The basic ESD models are Human Body model (HBM), Machine Mode (MM), and Charge Device Model (CDM). For the system-level ESD robustness, it is defined by different standards and specifications than component-level ESD requirements. International Electrotechnical Commission (IEC) 61000-4-2 has been used for the product and the Human Metal Model (HMM) has been used for the system at the wafer level. Increasingly stringent design specifications are forcing original equipment manufacturers (OEMs) to minimize the number of off-chip components. This is the case in emerging multifunction mobile, industrial, automotive and healthcare applications. It requires a high level of ESD robustness and the integrated circuit (IC) level, while finding ways to streamline the ESD characterization during early development cycle. To enable predicting the ESD performance of IC\u27s pins that are directly exposed to a system-level stress condition, a new the human metal model (HMM) test model has been introduced. In this work, a new testing methodology for product-level HMM characterization is introduced. This testing framework allows for consistently identifying ESD-induced failures in a product, substantially simplifying the testing process, and significantly reducing the product evaluation time during development cycle. It helps eliminates the potential inaccuracy provided by the conventional characterization methodology. For verification purposes, this method has been applied to detect the failures of two different products. Addition to the exploration of new characterization methodology that provides better accuracy, we also have looked into the protection devices itself. ICs for emerging high performance precision data acquisition and transceivers in industrial, automotive and wireless infrastructure applications require effective and ESD protection solutions. These circuits, with relatively high operating voltages at the Input/Output (I/O) pins, are increasingly being designed in low voltage Complementary Metal-Oxide-Semiconductor (CMOS) technologies to meet the requirements of low cost and large scale integration. A new dual-polarity SCR optimized for high bidirectional blocking voltages, high trigger current and low capacitance is realized in a sub 3-V, 180-nm CMOS process. This ESD device is designed for a specific application where the operating voltage at the I/O is larger than that of the core circuit. For instance, protecting high voltage swing I/Os in CMOS data acquisition system (DAS) applications. In this reference application, an array of thin film resistors voltage divider is directly connected to the interface pin, reducing the maximum voltage that is obtained at the core device input down to ± 1-5 V. Its ESD characteristics, including the trigger voltage and failure current, are compared against those of a typical CMOS-based SCR. Then, we have looked into the ESD protection designs into more advanced technology, the 28-nm CMOS. An ESD protection design builds on the multiple discharge-paths ESD cell concept and focuses the attention on the detailed design, optimization and realization of the in-situ ESD protection cell for IO pins with variable operation voltages. By introducing different device configurations fabricated in a 28-nm CMOS process, a greater flexibility in the design options and design trade-offs can be obtained in the proposed topology, thus achieving a higher integration and smaller cell size definition for multi-voltage compatibility interface ESD protection applications. This device is optimized for low capacitance and synthesized with the circuit IO components for in-situ ESD protection in communication interface applications developed in a 28-nm, high-k, and metal-gate CMOS technology. ESD devices have been used in different types of applications and also at different environment conditions, such as high temperature. At the last section of this research work, we have performed an investigation of several different ESD devices\u27 performance under various temperature conditions. And it has been shown that the variations of the device structure can results different ESD performance, and some devices can be used at the high temperature and some cannot. And this investigation also brings up a potential threat to the current ESD protection devices that they might be very vulnerable to the latch-up issue at the higher temperature range

On-die sensors for transient events

Failures caused by transient electromagnetic events like Electrostatic Discharge (ESD) are a major concern for embedded systems. The component often failing is an integrated circuit (IC). Determining which IC is affected in a multi-device system is a challenging task. Debugging errors often requires sophisticated lab setups which require intentionally disturbing and probing various parts of the system which might not be easily accessible. Opening the system and adding probes may change its response to the transient event, which further compounds the problem. On-die transient event sensors were developed that require relatively little area on die, making them inexpensive, they consume negligible static current, and do not interfere with normal operation of the IC. These circuits can be used to determine the pin involved and the level of the event in the event of a transient event affecting the IC, thus allowing the user to debug system-level transient events without modifying the system. The circuit and detection scheme design has been completed and verified in simulations with Cadence Virtuoso environment. Simulations accounted for the impact of the ESD protection circuits, parasitics from the I/O pin, package and I/O ring, and included a model of an ESD gun to test the circuit\u27s response to an ESD pulse as specified in IEC 61000-4-2. Multiple detection schemes are proposed. The final detection scheme consists of an event detector and a level sensor. The event detector latches on the presence of an event at a pad, to determine on which pin an event occurred. The level sensor generates current proportional to the level of the event. This current is converted to a voltage and digitized at the A/D converter to be read by the microprocessor. Detection scheme shows good performance in simulations when checked against process variations and different kind of events --Abstract, page iii

Correction due to finite speed of light in absolute gravimeters

Correction due to finite speed of light is among the most inconsistent ones in absolute gravimetry. Formulas reported by different authors yield corrections scattered up to 8 $\mu$Gal with no obvious reasons. The problem, though noted before, has never been studied, and nowadays the correction is rather postulated than rigorously proven. In this paper we make an attempt to revise the subject. Like other authors, we use physical models based on signal delays and the Doppler effect, however, in implementing the models we additionally introduce two scales of time associated with moving and resting reflectors, derive a set of rules to switch between the scales, and establish the equivalence of trajectory distortions as obtained from either time delay or distance progression. The obtained results enabled us to produce accurate correction formulas for different types of instruments, and to explain the differences in the results obtained by other authors. We found that the correction derived from the Doppler effect is accountable only for $\frac23$ of the total correction due to finite speed of light, if no signal delays are considered. Another major source of inconsistency was found in the tacit use of simplified trajectory models

Bump extraction algorithm for variable amplitude fatigue loading

This paper presents the development of a fatigue mission synthesis algorithm, called Wavelet Bump Extraction (WBE), for summarising long records of fatigue road load data. This algorithm is used to extract fatigue damaging events or bumps in the record that cause the majority of the fatigue damage, whilst preserving the load cycle sequences. Bumps are identified from characteristic frequency bands in the load spectrum using the 12th order Daubechies wavelet. The bumps are combined to produce a mission signal which has equivalent signal statistics and fatigue damage to the original signal. The WBE accuracy has been evaluated by observing the cycle sequence effects of the bump loadings. The WBE was compared with the time domain fatigue data editing method, so that the effectiveness of WBE can be verified. Using WBE, a substantial compression of the load-time history could be achieved for the purpose of accelerated fatigue tests in the automotive industry

Manipulation of entanglement sudden death in an all-optical setup

The unavoidable and irreversible interaction between an entangled quantum system and its environment causes decoherence of the individual qubits as well as degradation of the entanglement between them. Entanglement sudden death (ESD) is the phenomenon wherein disentanglement happens in finite time even when individual qubits decohere only asymptotically in time due to noise. Prolonging the entanglement is essential for the practical realization of entanglement-based quantum information and computation protocols. For this purpose, the local NOT operation in the computational basis on one or both qubits has been proposed. Here, we formulate an all-optical experimental set-up involving such NOT operations that can hasten, delay, or completely avert ESD, all depending on when it is applied during the process of decoherence. Analytical expressions for these are derived in terms of parameters of the initial state's density matrix, whether for pure or mixed entangled states. After a discussion of the schematics of the experiment, the problem is theoretically analyzed, and simulation results of such manipulations of ESD are presented