System-level transient ESD noise monitoring using off-chip and on-chip circuits

Department of Electrical EngineeringElectrostatic discharge (ESD) is defined as a sudden flow of electric charge between the objects with different electrostatic potentials caused by contact and breakdown of air gap or dielectric layer. In electronic systems, ESD is the remarkable critical issue for reliability of compact and complex integrated circuits (IC) and systems and must be deliberated from the initial design process for the safety of users and wasted cost from damaged products. To analyze the effects by the ESD events, the noise voltages inside the products induced by ESD events can be measured. However, the passive measurement method using cables has some limitations. Various on-die ESD detector circuits have previously been proposed to overcome the limits, providing the useful information for ESD noise analysis. But these circuits require lots of time and cost for design and fabrication, so it is hard to apply from the initial design process. In this thesis, two approaches are proposed for monitoring the system-level transient ESD noise as the further progress of previous researches regarding the detection of system-level transient ESD event. One is the usage of the off-chip ESD detection module including multiple detection circuits with different thresholds for characterizing the range of ESD noises. The proposed detection circuit utilizes the time delay by RC network and can sense the positive ESD events at power line. The sensing characteristics of the detection circuit against ESD event can be represented as a threshold curve. Utilizing the detection threshold curve, the range of ESD noises can be estimated without measurement. For more specific identification of ESD noise range, the detection module with multiple detection circuits are designed and the more exact estimation of noise range becomes possible, depending on which detection circuits sense the ESD event. The threshold curves of detection module are extracted using transmission line pulse (TLP) signals and validated through ESD current injection tests. After then, as an application to real situation, the system-level transient ESD noises in a commercial solid-state drive (SSD) storage system are characterized and analyzed. The other approach is the capturing the noise waveform itself like digital oscilloscope. Although the previous on-die ESD detector circuits and the proposed approach provide useful information, it is further demanded to obtain the accurate noise waveforms for more complete analysis. So, an on-die oscilloscope circuit including on-chip ESD event detectors is designed and fabricated in a 180-nm CMOS process. The validation of operation is performed, and the measurement results of on-chip ESD detectors are comparable to the results from circuit simulations. However, the ability of waveform capturing is under the designed specification due to several problems in circuit design process.clos

Measurement and Analysis of IC Jitters and Soft Failures due to System-level ESD

Department of Electrical EngineeringHuman touches to ground metal of electronic systems can cause electrostatic discharge (ESD)-induced soft failures without causing physical damage. If a number of data are lost due to ESD-induced noises, then a system freeze, fault, or reboot can occur, and user intervention is required to restore normal system operations. Such malfunction of a system is called system-level ESD soft failures that become more serious as the speed of electronic devices increases and their size becomes more compact. Achieving immunity of systems and integrated circuits (ICs) against soft failures due to system-level ESD is an important design goal. In this thesis, two specific circuits whose soft failures can be fatal to whole system are investigated. One of them is a delay-locked loop (DLL) and the other is a sense amplifier flip-flop (SAFF). The DLL is widely used to compensate the timing of high-speed data communications. The SAFF is commonly used as an input receiver for address and command in a DRAM. The DLL and SAFF were designed and fabricated in a 180-nm CMOS process. They are mounted in each simplified design of dual in-line memory module (DIMM) by chip on board (COB) assembly and the DIMMs are mounted on each simplified motherboard. The input and output voltages of the DLL under ESD-induced noises were measured, and the average values of peak-to-peak jitter and jitter durations of the DLL clock were obtained from repeated measurements. The effects of the VDD-GND decoupling capacitors and a bias decoupling capacitor were investigated. The measured DLL output are reproduced in SPICE simulations using the measured DLL input voltages, and the root causes of the jitter are investigated. Additionally, measurements are conducted in a frequency domain to find the relationship between the power-ground impedance and noises. The soft failures of the SAFF due to system-level ESD were investigated under the ESD injection level of 3, 5, and 8 kV. ESD test case without and with VDD-GND decoupling capacitors (de-caps) were investigated. The measurements were conducted 50 times with each test case above. The noise voltages and the soft failure ratio of the SAFF were obtained. SPICE simulation was conducted to validate the results by using measured noise voltages and root causes of the soft failures.clos

Air Force Institute of Technology Contributions to Air Force Research and Development, Calendar Year 1986

This report highlights AFIT\u27s contributions to Air Force research and development activities in 1986

Learning-Based Hardware Design for Data Acquisition Systems

This multidisciplinary research work aims to investigate the optimized information extraction from signals or data volumes and to develop tailored hardware implementations that trade-off the complexity of data acquisition with that of data processing, conceptually allowing radically new device designs. The mathematical results in classical Compressive Sampling (CS) support the paradigm of Analog-to-Information Conversion (AIC) as a replacement for conventional ADC technologies. The AICs simultaneously perform data acquisition and compression, seeking to directly sample signals for achieving specific tasks as opposed to acquiring a full signal only at the Nyquist rate to throw most of it away via compression. Our contention is that in order for CS to live up its name, both theory and practice must leverage concepts from learning. This work demonstrates our contention in hardware prototypes, with key trade-offs, for two different fields of application as edge and big-data computing. In the framework of edge-data computing, such as wearable and implantable ecosystems, the power budget is defined by the battery capacity, which generally limits the device performance and usability. This is more evident in very challenging field, such as medical monitoring, where high performance requirements are necessary for the device to process the information with high accuracy. Furthermore, in applications like implantable medical monitoring, the system performances have to merge the small area as well as the low-power requirements, in order to facilitate the implant bio-compatibility, avoiding the rejection from the human body. Based on our new mathematical foundations, we built different prototypes to get a neural signal acquisition chip that not only rigorously trades off its area, energy consumption, and the quality of its signal output, but also significantly outperforms the state-of-the-art in all aspects. In the framework of big-data and high-performance computation, such as in high-end servers application, the RF circuits meant to transmit data from chip-to-chip or chip-to-memory are defined by low power requirements, since the heat generated by the integrated circuits is partially distributed by the chip package. Hence, the overall system power budget is defined by its affordable cooling capacity. For this reason, application specific architectures and innovative techniques are used for low-power implementation. In this work, we have developed a single-ended multi-lane receiver for high speed I/O link in servers application. The receiver operates at 7 Gbps by learning inter-symbol interference and electromagnetic coupling noise in chip-to-chip communication systems. A learning-based approach allows a versatile receiver circuit which not only copes with large channel attenuation but also implements novel crosstalk reduction techniques, to allow single-ended multiple lines transmission, without sacrificing its overall bandwidth for a given area within the interconnect's data-path

Aeronautical Engineering - A special bibliography with indexes /supplement 1/

Annotated reference bibliography on aeronautical engineering document

Sustainability in design: now! Challenges and opportunities for design research, education and practice in the XXI century

Copyright @ 2010 Greenleaf PublicationsLeNS project funded by the Asia Link Programme, EuropeAid, European Commission

Diagnosing integration: applying complex systems thinking to develop practical tools for diagnosing institutional arrangements and their resilience in integrated water governance contexts

The developing water crisis is one of several emergent environmental crises that could produce catastrophic consequences for human health and wellbeing. Some biophysical scientists have described the world water crisis in terms of the resilience of various combinations of three problematic water management syndromes catchment by catchment throughout the globe, while some social scientists have described it as a crisis of governance. In this thesis I provide new insights into the resilience of integration institutions within the context of the governance of the Condamine catchment, at the headwaters of the Murray Darling Basin in Queensland. I develop these insights by applying a complex adaptive systems framework of governance, integration institutions, resilience and power; developing contextual-historical understandings of which, how and why integration institutions are being produced in this context; and by experimenting with systemically aligned theories of power. In the process I develop practical tools for working on integration institutions whilst being located within complex water governance systems. I apply combinations of five theoretical frameworks – complex adaptive systems; innovation systems; social-ecological systems; synchronisation framework; and, Foucault’s theory of power as a system of subject making – across four investigations. I collected data through ethnographic methods of observation; interview; and, the retrieval of artefacts (i.e. documents, photos and posters etc), whilst employing either instrumental case study or participatory action research methodologies. I analyse this data using discourse analysis and network analysis, and report the studies in the form of four journal articles which are in various stages of publication from submission through to being accepted and published. In this study I demonstrate the merit of thinking systemically about water governance institutions and the source of their resilience, and demonstrate the applicability of complex systems thinking. I reveal the fluid hybrid networks of actor relations that sustain governance systems, and show that the complex and dynamic interactions that sustain fluid hybrid networks are the source of institutional resilience. The results of the study challenges the use of short term interventions and innovation brokers within projects not grounded in systemic thinking. As the study was exploratory in nature several future research opportunities within a broader thematic turn towards complexity thinking in water and environmental governance research can be identified. More experimentation with the use of these tools and theoretical frameworks is required. Finally the assertion that the use of short term interventions and innovation brokers within projects not grounded in complex systems thinking may produce counter-intuitive outcomes and therefore delay institutional change is worthy of further attention

A brief overview of NASA Langley's research program in formal methods

An overview of NASA Langley's research program in formal methods is presented. The major goal of this work is to bring formal methods technology to a sufficiently mature level for use by the United States aerospace industry. Towards this goal, work is underway to design and formally verify a fault-tolerant computing platform suitable for advanced flight control applications. Also, several direct technology transfer efforts have been initiated that apply formal methods to critical subsystems of real aerospace computer systems. The research team consists of six NASA civil servants and contractors from Boeing Military Aircraft Company, Computational Logic Inc., Odyssey Research Associates, SRI International, University of California at Davis, and Vigyan Inc