5 research outputs found

    Innovative Techniques for Testing and Diagnosing SoCs

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    We rely upon the continued functioning of many electronic devices for our everyday welfare, usually embedding integrated circuits that are becoming even cheaper and smaller with improved features. Nowadays, microelectronics can integrate a working computer with CPU, memories, and even GPUs on a single die, namely System-On-Chip (SoC). SoCs are also employed on automotive safety-critical applications, but need to be tested thoroughly to comply with reliability standards, in particular the ISO26262 functional safety for road vehicles. The goal of this PhD. thesis is to improve SoC reliability by proposing innovative techniques for testing and diagnosing its internal modules: CPUs, memories, peripherals, and GPUs. The proposed approaches in the sequence appearing in this thesis are described as follows: 1. Embedded Memory Diagnosis: Memories are dense and complex circuits which are susceptible to design and manufacturing errors. Hence, it is important to understand the fault occurrence in the memory array. In practice, the logical and physical array representation differs due to an optimized design which adds enhancements to the device, namely scrambling. This part proposes an accurate memory diagnosis by showing the efforts of a software tool able to analyze test results, unscramble the memory array, map failing syndromes to cell locations, elaborate cumulative analysis, and elaborate a final fault model hypothesis. Several SRAM memory failing syndromes were analyzed as case studies gathered on an industrial automotive 32-bit SoC developed by STMicroelectronics. The tool displayed defects virtually, and results were confirmed by real photos taken from a microscope. 2. Functional Test Pattern Generation: The key for a successful test is the pattern applied to the device. They can be structural or functional; the former usually benefits from embedded test modules targeting manufacturing errors and is only effective before shipping the component to the client. The latter, on the other hand, can be applied during mission minimally impacting on performance but is penalized due to high generation time. However, functional test patterns may benefit for having different goals in functional mission mode. Part III of this PhD thesis proposes three different functional test pattern generation methods for CPU cores embedded in SoCs, targeting different test purposes, described as follows: a. Functional Stress Patterns: Are suitable for optimizing functional stress during I Operational-life Tests and Burn-in Screening for an optimal device reliability characterization b. Functional Power Hungry Patterns: Are suitable for determining functional peak power for strictly limiting the power of structural patterns during manufacturing tests, thus reducing premature device over-kill while delivering high test coverage c. Software-Based Self-Test Patterns: Combines the potentiality of structural patterns with functional ones, allowing its execution periodically during mission. In addition, an external hardware communicating with a devised SBST was proposed. It helps increasing in 3% the fault coverage by testing critical Hardly Functionally Testable Faults not covered by conventional SBST patterns. An automatic functional test pattern generation exploiting an evolutionary algorithm maximizing metrics related to stress, power, and fault coverage was employed in the above-mentioned approaches to quickly generate the desired patterns. The approaches were evaluated on two industrial cases developed by STMicroelectronics; 8051-based and a 32-bit Power Architecture SoCs. Results show that generation time was reduced upto 75% in comparison to older methodologies while increasing significantly the desired metrics. 3. Fault Injection in GPGPU: Fault injection mechanisms in semiconductor devices are suitable for generating structural patterns, testing and activating mitigation techniques, and validating robust hardware and software applications. GPGPUs are known for fast parallel computation used in high performance computing and advanced driver assistance where reliability is the key point. Moreover, GPGPU manufacturers do not provide design description code due to content secrecy. Therefore, commercial fault injectors using the GPGPU model is unfeasible, making radiation tests the only resource available, but are costly. In the last part of this thesis, we propose a software implemented fault injector able to inject bit-flip in memory elements of a real GPGPU. It exploits a software debugger tool and combines the C-CUDA grammar to wisely determine fault spots and apply bit-flip operations in program variables. The goal is to validate robust parallel algorithms by studying fault propagation or activating redundancy mechanisms they possibly embed. The effectiveness of the tool was evaluated on two robust applications: redundant parallel matrix multiplication and floating point Fast Fourier Transform

    Test and Diagnosis of Integrated Circuits

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    The ever-increasing growth of the semiconductor market results in an increasing complexity of digital circuits. Smaller, faster, cheaper and low-power consumption are the main challenges in semiconductor industry. The reduction of transistor size and the latest packaging technology (i.e., System-On-a-Chip, System-In-Package, Trough Silicon Via 3D Integrated Circuits) allows the semiconductor industry to satisfy the latest challenges. Although producing such advanced circuits can benefit users, the manufacturing process is becoming finer and denser, making chips more prone to defects.The work presented in the HDR manuscript addresses the challenges of test and diagnosis of integrated circuits. It covers:- Power aware test;- Test of Low Power Devices;- Fault Diagnosis of digital circuits

    Conception d'une plateforme de tests de circuits d'intégration directe sur tranche

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    L'intégration directe sur tranche est une technique de fabrication de puces électroniques pour laquelle une seule puce couvre la grande majorité de la surface d'une tranche. Cette technique présente un très grand potentiel d'intégration mais comporte des risques technologiques importants. Malgré ces risques, la compagnie Hyperchip croit qu'il serait possible d'améliorer son produit en utilisant une telle technologie. Dans le cadre d'une coopération universitaire, Hyperchip a conçu un certain nombre de puces qui contiennent des structures de tests ainsi que des stratégies pour contourner les différents problèmes potentiels. Ces puces n'ont, jusqu'à présent, jamais été vérifiées. Dans le but de valider les idées implantées dans ces démonstrateurs, une carte de test est nécessaire. Cette carte doit être assez flexible pour permettre la vérification de tous les démonstrateurs présents et futurs. Il existe plusieurs cartes sur le marché mais aucune d'entre elles ne satisfait l'exigence du nombre de ports demandés par la spécification préliminaire. La conception d'une carte dédiée est donc requise. Ce projet porte sur la conception de cette carte de test dédiée: Erinyes. Les spécifications de deux démonstrateurs seront utilisées pour guider la conception: le démo 4 et le démo 5. Le démo 4 présente un mécanisme de tolérance aux défectuosités de fabrication des puces d'intégration directe sur tranche. Le démo 5 quant à lui, explore les problèmes liés à la diaphonie et à la température. Étant donné le contexte particulier entourant ce projet, son étendue et ses contributions ont été limitées à la conception logique du matériel, à la programmation des circuits intégrés de type FPGA et à la planification des modifications nécessaires au système d'exploitation [mu]CLinux

    Design and application of electromechanical actuators for deep space missions

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    This progress report documents research and development efforts performed from August 16, 1993 through August 15, 1994 on NASA Grant NAG8-240, 'Design and Application of Electromechanical Actuators for Deep Space Missions.' Since the submission of our last progress report in February 1994, our efforts have been almost entirely focused on final construction of the test stand and experiment design. Hence, this report is dedicated solely to these topics. However, updates on our research personnel and our health monitoring and fault management efforts are provided in this summary. Following this executive summary are two report sections. The first is devoted to the motor drive being constructed for the test stand. The thrust of the next section is the mechanical and hydraulic design and construction based on the planned experimental requirements. Following both major sections are three appendices

    The Fifth NASA Symposium on VLSI Design

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    The fifth annual NASA Symposium on VLSI Design had 13 sessions including Radiation Effects, Architectures, Mixed Signal, Design Techniques, Fault Testing, Synthesis, Signal Processing, and other Featured Presentations. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The presentations share insights into next generation advances that will serve as a basis for future VLSI design
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