Engineering at San Jose State University, Fall 2012

https://scholarworks.sjsu.edu/engr_news/1010/thumbnail.jp

Innovation Offshoring:Asia's Emerging Role in Global Innovation Networks

Most analysts agree that critical ingredients for economic growth, competitiveness, and welfare in the United States have been policies that encourage strong investment in research and development (R&D) and innovation. In addition, there is a general perception that technological innovation must be based in the United States to remain a pillar of the American economy. Over the past decade, however, the rise of Asia as an important location for "innovation offshoring" has begun to challenge these familiar notions. Based on original research, this report demonstrates that innovation offshoring is driven by profound changes in corporate innovation management as well as by the globalization of markets for technology and knowledge workers. U.S. companies are at the forefront of this trend, but Asian governments and firms are playing an increasingly active role as promoters and new sources of innovation. Innovation offshoring has created a competitive challenge of historic proportions for the United States, requiring the nation to respond with a new national strategy. This report recommends that such a strategy include the following elements: output forecasting techniques ... Improve access to and collection of innovation-related data to inform the national policy debate; Address "home-made" causes of innovation offshoring by sustaining and building upon existing strengths of the U.S. innovation system; Support corporate innovation by (1) providing tax incentives to spur early-state investments in innovation start-ups and (2) reforming the U.S. patent system so it is more accessible to smaller inventors and innovators; and Upgrade the U.S. talent pool of knowledge workers by (1) providing incentives to study science and engineering, (2) encouraging the development of management, interpretive, cross-cultural, and other "soft" capabilities, and (3) encouraging immigration of highly skilled workers.Innovation Networks, Innovation Offshoring, Asia

Lessons from an Open Source Business

Creating a successful company is difficult; but creating a successful company, a successful open source project, and a successful ecosystem all at the same time is much more difficult. This article takes a retrospective look at some of the lessons we have learned in building BigBlueButton, an open source web conferencing system for distance education, and in building Blindside Networks, a company following the traditional business model of providing support and services to paying customers. Our main message is that the focus must be on creating a successful open source project first, for without it, no company in the ecosystem can flourish

From Microelectronics to Nanoelectronics: Introducing Nanotechnology to VLSI Curricula

© 2011 by ASEEIn the past decades, VLSI industries constantly shrank the size of transistors, so that more and more transistors can be built into the same chip area to make VLSI more and more powerful in its functions. As the typical feature size of CMOS VLSI is shrunk into deep submicron domain, nanotechnology is the next step in order to maintain Moore’s law for several more decades. Nanotechnology not only further improves the resolution in traditional photolithography process, but also introduces many brand-new fabrication strategies, such as bottom-up molecular self-assembly. Nanotechnology is also enabling many novel devices and circuit architectures which are totally different from current microelectronics circuits, such as quantum computing, nanowire crossbar circuits, spin electronics, etc. Nanotechnology is bringing another technology revolution to traditional CMOS VLSI technology. In order to train students to meet the quickly-increasing industry demand for nextgeneration nanoelectronics engineers, we are making efforts to introduce nanotechnology into our VLSI curricula. We have developed a series of VLSI curricula which include CPE/EE 448D - Introduction to VLSI, EE 548 - Low Power VLSI Circuit Design, EE 458 - Analog VLSI Circuit Design, EE 549 - VLSI Testing, etc. Furthermore, we developed a series of micro and nanotechnology related courses, such as EE 451 - Nanotechnology, EE 448 - Microelectronic Fabrication, EE 446 – MEMS (Microelectromechanical Systems). We introduce nanotechnology into our VLSI curricula, and teach the students about various devices, fabrication processes, circuit architectures, design and simulation skills for future nanotechnology-based nanoelectronic circuits. Some examples are nanowire crossbar circuit architecture, carbon-nanotube based nanotransistor, single-electron transistor, spintronics, quantum computing, bioelectronic circuits, etc. Students show intense interest in these exciting topics. Some students also choose nanoelectronics as the topic for their master project/thesis, and perform successful research in the field. The program has attracted many graduate students into the field of nanoelectronics

Hardware Certification for Real-time Safety-critical Systems: State of the Art

This paper discusses issues related to the RTCA document DO-254 Design Assurance Guidance for Airborne Electronic Hardware and its consequences for hardware certification. In particular, problems related to circuits’ compliance with DO-254 in avionics and other industries are considered. Extensive literature review of the subject is given, including current views on and experiences of chip manufacturers and EDA industry with qualification of hardware design tools, including formal approaches to hardware verification. Some results of the authors’ own study on tool qualification are presented

Solar Energy Harvesting to Improve Capabilities of Wearable Devices

The market of wearable devices has been growing over the past decades. Smart wearables are usually part of IoT (Internet of things) systems and include many functionalities such as physiological sensors, processing units and wireless communications, that are useful in fields like healthcare, activity tracking and sports, among others. The number of functions that wearables have are increasing all the time. This result in an increase in power consumption and more frequent recharges of the battery. A good option to solve this problem is using energy harvesting so that the energy available in the environment is used as a backup power source. In this paper, an energy harvesting system for solar energy with a flexible battery, a semi-flexible solar harvester module and a BLE (Bluetooth® Low Energy) microprocessor module is presented as a proof-of-concept for the future integration of solar energy harvesting in a real wearable smart device. The designed device was tested under different circumstances to estimate the increase in battery lifetime during common daily routines. For this purpose, a procedure for testing energy harvesting solutions, based on solar energy, in wearable devices has been proposed. The main result obtained is that the device could permanently work if the solar cells received a significant amount of direct sunlight for 6 h every day. Moreover, in real-life scenarios, the device was able to generate a minimum and a maximum power of 27.8 mW and 159.1 mW, respectively. For the wearable system selected, Bindi, the dynamic tests emulating daily routines has provided increases in the state of charge from 19% (winter cloudy days, 4 solar cells) to 53% (spring sunny days, 2 solar cells). Keywords: energy harvesting; internet of things; physiologicalThis research was funded by the Department of Research and Innovation of Madrid Regional Authority, in the EMPATIA-CM research project (reference Y2018/TCS-5046). This work has been partially supported by the European Union—NextGenerationEU, with the SAPIENTIAE4BINDI project “Proof of Concept” 2021. (Ref: PDC2021-121071-I00/AEI/10.13039/501100011033). This work has been supported by the Madrid Government (Comunidad de Madrid-Spain) under the Multiannual Agreement with UC3M in the line of Excellence of University Professors (EPUC3M26), and in the context of the V PRICIT (Regional Programme of Research and Technological Innovation)

CAD methodologies for low power and reliable 3D ICs

The main objective of this dissertation is to explore and develop computer-aided-design (CAD) methodologies and optimization techniques for reliability, timing performance, and power consumption of through-silicon-via(TSV)-based and monolithic 3D IC designs. The 3D IC technology is a promising answer to the device scaling and interconnect problems that industry faces today. Yet, since multiple dies are stacked vertically in 3D ICs, new problems arise such as thermal, power delivery, and so on. New physical design methodologies and optimization techniques should be developed to address the problems and exploit the design freedom in 3D ICs. Towards the objective, this dissertation includes four research projects. The first project is on the co-optimization of traditional design metrics and reliability metrics for 3D ICs. It is well known that heat removal and power delivery are two major reliability concerns in 3D ICs. To alleviate thermal problem, two possible solutions have been proposed: thermal-through-silicon-vias (T-TSVs) and micro-fluidic-channel (MFC) based cooling. For power delivery, a complex power distribution network is required to deliver currents reliably to all parts of the 3D IC while suppressing the power supply noise to an acceptable level. However, these thermal and power networks pose major challenges in signal routability and congestion. In this project, a co-optimization methodology for signal, power, and thermal interconnects in 3D ICs is presented. The goal of the proposed approach is to improve signal, thermal, and power noise metrics and to provide fast and accurate design space explorations for early design stages. The second project is a study on 3D IC partition. For a 3D IC, the target circuit needs to be partitioned into multiple parts then mapped onto the dies. The partition style impacts design quality such as footprint, wirelength, timing, and so on. In this project, the design methodologies of 3D ICs with different partition styles are demonstrated. For the LEON3 multi-core microprocessor, three partitioning styles are compared: core-level, block-level, and gate-level. The design methodologies for such partitioning styles and their implications on the physical layout are discussed. Then, to perform timing optimizations for 3D ICs, two timing constraint generation methods are demonstrated that lead to different design quality. The third project is on the buffer insertion for timing optimization of 3D ICs. For high performance 3D ICs, it is crucial to perform thorough timing optimizations. Among timing optimization techniques, buffer insertion is known to be the most effective way. The TSVs have a large parasitic capacitance that increases the signal slew and the delay on the downstream. In this project, a slew-aware buffer insertion algorithm is developed that handles full 3D nets and considers TSV parasitics and slew effects on delay. Compared with the well-known van Ginneken algorithm and a commercial tool, the proposed algorithm finds buffering solutions with lower delay values and acceptable runtime overhead. The last project is on the ultra-high-density logic designs for monolithic 3D ICs. The nano-scale 3D interconnects available in monolithic 3D IC technology enable ultra-high-density device integration at the individual transistor-level. The benefits and challenges of monolithic 3D integration technology for logic designs are investigated. First, a 3D standard cell library for transistor-level monolithic 3D ICs is built and their timing and power behavior are characterized. Then, various interconnect options for monolithic 3D ICs that improve design quality are explored. Next, timing-closed, full-chip GDSII layouts are built and iso-performance power comparisons with 2D IC designs are performed. Important design metrics such as area, wirelength, timing, and power consumption are compared among transistor-level monolithic 3D, gate-level monolithic 3D, TSV-based 3D, and traditional 2D designs.PhDCommittee Chair: Lim, Sung Kyu; Committee Member: Bakir, Muhannad; Committee Member: Kim, Hyesoon; Committee Member: Lee, Hsien-Hsin; Committee Member: Mukhopadhyay, Saiba