114 research outputs found
Study Of Nanoscale Cmos Device And Circuit Reliability
The development of semiconductor technology has led to the significant scaling of the transistor dimensions -The transistor gate length drops down to tens of nanometers and the gate oxide thickness to 1 nm. In the future several years, the deep submicron devices will dominate the semiconductor industry for the high transistor density and the corresponding performance enhancement. For these devices, the reliability issues are the first concern for the commercialization. The major reliability issues caused by voltage and/or temperature stress are gate oxide breakdown (BD), hot carrier effects (HCs), and negative bias temperature instability (NBTI). They become even more important for the nanoscale CMOS devices, because of the high electrical field due to the small device size and high temperature due to the high transistor densities and high-speed performances. This dissertation focuses on the study of voltage and temperature stress-induced reliability issues in nanoscale CMOS devices and circuits. The physical mechanisms for BD, HCs, and NBTI have been presented. A practical and accurate equivalent circuit model for nanoscale devices was employed to simulate the RF performance degradation in circuit level. The parameter measurement and model extraction have been addressed. Furthermore, a methodology was developed to predict the HC, TDDB, and NBTI effects on the RF circuits with the nanoscale CMOS. It provides guidance for the reliability considerations of the RF circuit design. The BD, HC, and NBTI effects on digital gates and RF building blocks with the nanoscale devices low noise amplifier, oscillator, mixer, and power amplifier, have been investigated systematically. The contributions of this dissertation include: It provides a thorough study of the reliability issues caused by voltage and/or temperature stresses on nanoscale devices from device level to circuit level; The more real voltage stress case high frequency (900 MHz) dynamic stress, has been first explored and compared with the traditional DC stress; A simple and practical analytical method to predict RF performance degradation due to voltage stress in the nanoscale devices and RF circuits was given based on the normalized parameter degradations in device models. It provides a quick way for the designers to evaluate the performance degradations; Measurement and model extraction technologies, special for the nanoscale MOSFETs with ultra-thin, ultra-leaky gate oxide, were addressed and employed for the model establishments; Using the present existing computer-aided design tools (Cadence, Agilent ADS) with the developed models for performance degradation evaluation due to voltage or/and temperature stress by simulations provides a potential way that industry could use to save tens of millions of dollars annually in testing costs. The world now stands at the threshold of the age of nanotechnology, and scientists and engineers have been exploring here for years. The reliability is the first challenge for the commercialization of the nanoscale CMOS devices, which will be further downscaling into several tens or ten nanometers. The reliability is no longer the post-design evaluation, but the pre-design consideration. The successful and fruitful results of this dissertation, from device level to circuit level, provide not only an insight on how the voltage and/or temperature stress effects on the performances, but also methods and guidance for the designers to achieve more reliable circuits with nanoscale MOSFETs in the future
Low Power Cmos Circuit Design And Reliability Analysis For Wireless Me
A sensor node \u27AccuMicroMotion\u27 is proposed that has the ability to detect motion in 6 degrees of freedom for the application of physiological activity monitoring. It is expected to be light weight, low power, small and cheap. The sensor node may collect and transmit 3 axes of acceleration and 3 axes of angular rotation signals from MEMS transducers wirelessly to a nearby base station while attached to or implanted in human body. This dissertation proposes a wireless electronic system-on-a-single-chip to implement the sensor in a traditional CMOS process. The system is low power and may operate 50 hours from a single coin cell battery. A CMOS readout circuit, an analog to digital converter and a wireless transmitter is designed to implement the proposed system. In the architecture of the \u27AccuMicroMotion\u27 system, the readout circuit uses chopper stabilization technique and can resolve DC to 1 KHz and 200 nV signals from MEMS transducers. The base band signal is digitized using a 10-bit successive approximation register analog to digital converter. Digitized outputs from up to nine transducers can be combined in a parallel to serial converter for transmission by a 900 MHz RF transmitter that operates in amplitude shift keying modulation technique. The transmitter delivers a 2.2 mW power to a 50 Ă antenna. The system consumes an average current of 4.8 mA from a 3V supply when 6 sensors are in operation and provides an overall 60 dB dynamic range. Furthermore, in this dissertation, a methodology is developed that applies accelerated electrical stress on MOS devices to extract BSIM3 models and RF parameters through measurements to perform comprehensive study, analysis and modeling of several analog and RF circuits under hot carrier and breakdown degradation
Study Of Design For Reliability Of Rf And Analog Circuits
Due to continued device dimensions scaling, CMOS transistors in the nanometer regime have resulted in major reliability and variability challenges. Reliability issues such as channel hot electron injection, gate dielectric breakdown, and negative bias temperature instability (NBTI) need to be accounted for in the design of robust RF circuits. In addition, process variations in the nanoscale CMOS transistors are another major concern in todayâs circuits design. An adaptive gate-source biasing scheme to improve the RF circuit reliability is presented in this work. The adaptive method automatically adjusts the gate-source voltage to compensate the reduction in drain current subjected to various device reliability mechanisms. A class-AB RF power amplifier shows that the use of a source resistance makes the power-added efficiency robust against threshold voltage and mobility variations, while the use of a source inductance is more reliable for the input third-order intercept point. A RF power amplifier with adaptive gate biasing is proposed to improve the circuit device reliability degradation and process variation. The performances of the power amplifier with adaptive gate biasing are compared with those of the power amplifier without adaptive gate biasing technique. The adaptive gate biasing makes the power amplifier more resilient to process variations as well as the device aging such as mobility and threshold voltage degradation. Injection locked voltage-controlled oscillators (VCOs) have been examined. The VCOs are implemented using TSMC 0.18 ”m mixed-signal CMOS technology. The injection locked oscillators have improved phase noise performance than free running oscillators. iv A differential Clapp-VCO has been designed and fabricated for the evaluation of hot electron reliability. The differential Clapp-VCO is formed using cross-coupled nMOS transistors, on-chip transformers/inductors, and voltage-controlled capacitors. The experimental data demonstrate that the hot carrier damage increases the oscillation frequency and degrades the phase noise of Clapp-VCO. A p-channel transistor only VCO has been designed for low phase noise. The simulation results show that the phase noise degrades after NBTI stress at elevated temperature. This is due to increased interface states after NBTI stress. The process variability has also been evaluated
Novel Current-Mode Sensor Interfacing and Radio Blocks for Cell Culture Monitoring
Since 2004 Imperial College has been developing the worldâs first application-specific
instrumentation aiming at the on-line, in-situ, physiochemical monitoring of adult stem
cell cultures. That effort is internationally known as the âIntelligent Stem Cell Culture
Systemsâ (ISCCS) project. The ISCCS platform is formed by the functional integration
of biosensors, interfacing electronics and bioreactors. Contrary to the PCB-level
ISCCS platform the work presented in this thesis relates to the realization of a miniaturized
cell culture monitoring platform. Specifically, this thesis details the synthesis and
fabrication of pivotal VLSI circuit blocks suitable for the construction of a miniaturized
microelectronic cell monitoring platform. The thesis is composed of two main parts.
The first part details the design and operation of a two-stage current-input currentoutput
topology suitable for three-electrode amperometric sensor measurements. The
first stage is a CMOS-dual rail-class AB-current conveyor providing a low impedancevirtual
ground node for a current input. The second stage is a novel hyperbolic-sinebased
externally-linear internally-non-linear current amplification stage. This stage
bases its operation upon the compressive sinhâ1 conversion of the interfaced current
to an intermediate auxiliary voltage and the subsequent sinh expansion of the same
voltage. The proposed novel topology has been simulated for current-gain values ranging
from 10 to 1000 using the parameters of the commercially available 0.8ÎŒm AMS
CMOS process. Measured results from a chip fabricated in the same technology are also
reported. The proposed interfacing/amplification architecture consumes 0.88-95ÎŒW. The second part describes the design and practical evaluation of a 13.56MHz frequency
shift keying (FSK) short-range (5cm) telemetry link suitable for the monitoring of incubated
cultures. Prior to the design of the full FSK radio system, a pair of 13.56MHz
antennae are characterized experimentally. The experimental S-parameter-value determination
of the 13.56MHz wireless link is incorporated into the Cadence Design
Framework allowing a high fidelity simulation of the reported FSK radio. The transmitter
of the proposed system is a novel multi-tapped seven-stage ring-oscillator-based
VCO whereas the core of the receiver is an appropriately modified phase locked loop
(PLL). Simulated and measured results from a 0.8ÎŒm CMOS technology chip are reported
Analysis and design of wideband voltage controlled oscillators using self-oscillating active inductors.
Voltage controlled oscillators (VCOs) are essential components of RF circuits used in
transmitters and receivers as sources of carrier waves with variable frequencies. This, together
with a rapid development of microelectronic circuits, led to an extensive research
on integrated implementations of the oscillator circuits. One of the known approaches
to oscillator design employs resonators with active inductors electronic circuits simulating
the behavior of passive inductors using only transistors and capacitors. Such
resonators occupy only a fraction of the silicon area necessary for a passive inductor,
and thus allow to use chip area more eectively. The downsides of the active inductor
approach include: power consumption and noise introduced by transistors.
This thesis presents a new approach to active inductor oscillator design using selfoscillating
active inductor circuits. The instability necessary to start oscillations is
provided by the use of a passive RC network rather than a power consuming external
circuit employed in the standard oscillator approach. As a result, total power consumption
of the oscillator is improved. Although, some of the active inductors with
RC circuits has been reported in the literature, there has been no attempt to utilise
this technique in wideband voltage controlled oscillator design. For this reason, the
dissertation presents a thorough investigation of self-oscillating active inductor circuits,
providing a new set of design rules and related trade-os. This includes: a complete
small signal model of the oscillator, sensitivity analysis, large signal behavior of the circuit
and phase noise model. The presented theory is conrmed by extensive simulations
of wideband CMOS VCO circuit for various temperatures and process variations. The obtained results prove that active inductor oscillator performance is obtained without
the use of standard active compensation circuits. Finally, the concept of self-oscillating
active inductor has been employed to simple and fast OOK (On-Off Keying) transmitter
showing energy eciency comparable to the state of the art implementations reported
in the literature
Impedance matching and DC-DC converter designs for tunable radio frequency based mobile telecommunication systems
Tunability and adaptability for radio frequency (RF) front-ends are highly desirable because
they not only enhance functionality and performance but also reduce the circuit size and cost.
This thesis presents a number of novel design strategies in DC-DC converters, impedance
networks and adaptive algorithms for tunable and adaptable RF based mobile
telecommunication systems. Specifically, the studies are divided into three major directions:
(a) high voltage switch controller based DC-DC converters for RF switch actuation; (b)
impedance network designs for impedance transformation of RF switches; and (c) adaptive
algorithms for determining the required impedance states at the RF switches.
In the first stage, two-phase step-up switched-capacitor (SC) DC-DC converters are
explored. The SC converter has a simple control method and a reduced physical volume. The
research investigations started with the linear and the non-linear voltage gain topologies. The
non-linear voltage gain topology provides a higher voltage gain in a smaller number of
stages compared to the linear voltage gain topology. Amongst the non-linear voltage gain
topologies, a Fibonacci SC converter has been identified as having lower losses and a higher
conversion ratio compared to other topologies. However, the implementation of a high
voltage (HV) gain Fibonacci SC converter is complex due to the requirement of widely
different gate voltages for the transistors in the Fibonacci converter. Gate driving strategies
have been proposed that only require a few auxiliary transistors in order to provide the
required boosted voltages for switching the transistors on and off. This technique reduces the
design complexity and increases the reliability of the HV Fibonacci SC converter.
For the linear voltage gain topology, a high performance complementary-metaloxide-
semiconductor (CMOS) based SC DC-DC converter has been proposed in this work.
The HV SC DC-DC converter has been designed in low voltage (LV) transistors technology
in order to achieve higher voltage gain. Adaptive biasing circuits have been proposed to
eliminate the leakage current, hence avoiding latch-up which normally occurs with low
voltage transistors when they are used in a high voltage design. Thus, the SC DC-DC
converter achieves more than 25% higher boosted voltage compared to converters that use
HV transistors. The proposed design provides a 40% power reduction through the charge
recycling circuit that reduces the effect of non-ideality in integrated HV capacitors.
Moreover, the SC DC-DC converter achieves a 45% smaller area than the conventional
converter through optimising the design parameters. In the second stage, the impedance network designs for transforming the impedance
of RF switches to the maximum achievable impedance tuning region are investigated. The
maximum achievable tuning region is bounded by the fundamental properties of the selected
impedance network topology and by the tunable values of the RF switches that are variable
over a limited range. A novel design technique has been proposed in order to achieve the
maximum impedance tuning region, through identifying the optimum electrical distance
between the RF switches at the impedance network. By varying the electrical distance
between the RF switches, high impedance tuning regions are achieved across multi
frequency standards. This technique reduces the cost and the insertion loss of an impedance
network as the required number of RF switches is reduced. The prototype demonstrates high
impedance coverages at LTE (700MHz), GSM (900MHz) and GPS (1575MHz).
Integration of a tunable impedance network with an antenna for frequency-agility at
the RF front-end has also been discussed in this work. The integrated system enlarges the
bandwidth of a patch antenna by four times the original bandwidth and also improves the
antenna return loss. The prototype achieves frequency-agility from 700MHz to 3GHz. This
work demonstrates that a single transceiver with multi frequency standards can be realised
by using a tunable impedance network.
In the final stage, improvement to an adaptive algorithm for determining the
impedance states at the RF switches has been proposed. The work has resulted in one more
novel design techniques which reduce the search time in the algorithm, thus minimising the
risk of data loss during the impedance tuning process. The approach reduces the search time
by more than an order of magnitude by exploiting the relationships among the mass springâs
coefficient values derived from the impedance network parameters, thereby significantly
reducing the convergence time of the algorithm. The algorithm with the proposed technique
converges in less than half of the computational time compared to the conventional
approach, hence significantly improving the search time of the algorithm.
The design strategies proposed in this work contribute towards the realisation of
tunable and adaptable RF based mobile telecommunication systems
SOI RF-MEMS Based Variable Attenuator for Millimeter-Wave Applications
The most-attractive feature of microelectromechanical systems (MEMS) technology is that it enables the integration of a whole system on a single chip, leading to positive effects on the performance, reliability and cost. MEMS has made it possible to design IC-compatible radio frequency (RF) devices for wireless and satellite communication systems. Recently, with the advent of 5G, there is a huge market pull towards millimeter-wave devices. Variable attenuators are widely employed for adjusting signal levels in high frequency equipment. RF circuits such as automatic gain control amplifiers, broadband vector modulators, full duplex wireless systems, and radar systems are some of the primary applications of variable attenuators.
This thesis describes the development of a millimeter-wave RF MEMS-based variable attenuator implemented by monolithically integrating Coplanar Waveguide (CPW) based hybrid couplers with lateral MEMS varactors on a SiliconâonâInsulator (SOI) substrate. The MEMS varactor features a Chevron type electrothermal actuator that controls the lateral movement of a thick plate, allowing precise change in the capacitive loading on a CPW line leading to a change in isolation between input and output. Electrothermal actuators have been employed in the design instead of electrostatic ones because they can generate relatively larger in-line deflection and force within a small footprint. They also provide the advantage of easy integration with other electrical micro-systems on the same chip, since their fabrication process is compatible with general IC fabrication processes. The development of an efficient and reliable actuator has played an important role in the performance of the proposed design of MEMS variable attenuator. A Thermoreflectance (TR) imaging system is used to acquire the surface temperature profiles of the electrothermal actuator employed in the design, so as to study the temperature distribution, displacement and failure analysis of the Chevron actuator.
The 60 GHz variable attenuator was developed using a custom fabrication process on an SOI substrate with a device footprint of 3.8 mm x 3.1 mm. The fabrication process has a high yield due to the high-aspect-ratio single-crystal-silicon structures, which are free from warping, pre-deformation and sticking during the wet etching process. The SOI wafer used has a high resistivity (HR) silicon (Si) handle layer that provides an excellent substrate material for RF communication devices at microwave and millimeter wave frequencies. This low-cost fabrication process provides the flexibility to extend this module and implement more complex RF signal conditioning functions. It is thus an appealing candidate for realizing a wide range of reconfigurable RF devices. The measured RF performance of the 60 GHz variable attenuator shows that the device exhibits attenuation levels (|S21|) ranging from 10 dB to 25 dB over a bandwidth of 4 GHz and a return loss of better than 20 dB.
The thesis also presents the design and implementation of a MEMS-based impedance tuner on a Silicon-On-Insulator (SOI) substrate. The tuner is comprised of four varactors monolithically integrated with CPW lines. Chevron actuators control the lateral motion of capacitive thick plates used as contactless lateral MEMS varactors, achieving a capacitance range of 0.19 pF to 0.8 pF. The improvement of the Smith chart coverage is achieved by proper choice of the electrical lengths of the CPW lines and precise control of the lateral motion of the capacitive plates. The measured results demonstrate good impedance matching coverage, with an insertion loss of 2.9 dB.
The devices presented in this thesis provide repeatable and reliable operation due to their robust, thick-silicon structures. Therefore, they exhibit relatively low residual stress and are free from stiction and micro-welding problems
Design of Frequency divider with voltage vontrolled oscillator for 60 GHz low power phase-locked loops in 65 nm RF CMOS
Increasing memory capacity in mobile devices, is driving the need of high-data rates equipment. The 7 GHz band around 60 GHz provides the opportunity for multi-gigabit/sec wireless communication. It is a real opportunity for developing next generation of High-Definition (HD) devices. In the last two decades there was a great proliferation of Voltage Controlled Oscillator (VCO) and Frequency Divider (FD) topologies in RF ICs on silicon, but reaching high performance VCOs and FDs operating at 60 GHz is in today's technology a great challenge. A key reason is the inaccuracy of CMOS active and passive device models at mm-W. Three critical issues still constitute research objectives at 60 GHz in CMOS: generation of the Local Oscillator (LO) signal (1), division of the LO signal for the Phase-Locked Loop (PLL) closed loop (2) and distribution of the LO signal (3). In this Thesis, all those three critical issues are addressed and experimentally faced-up: a divide-by-2 FD for a PLL of a direct-conversion transceiver operating at mm-W frequencies in 65 nm RF CMOS technology has been designed. Critical issues such as Process, Voltage and Temperature (PVT) variations, Electromagnetic (EM) simulations and power consumption are addressed to select and design a FD with high frequency dividing range. A 60 GHz VCO is co-designed and integrated in the same die, in order to provide the FD with mm-W input signal. VCOs and FDs play critical roles in the PLL. Both of them constitute the PLL core components and they would need co-design, having a big impact in the overall performance especially because they work at the highest frequency in the PLL. Injection Locking FD (ILFD) has been chosen as the optimum FD topology to be inserted in the control loop of mm-W PLL for direct-conversion transceiver, due to the high speed requirements and the power consumption constraint. The drawback of such topology is the limited bandwidth, resulting in narrow Locking Range (LR) for WirelessHDTM applications considering the impact of PVT variations. A simulation methodology is presented in order to analyze the ILFD locking state, proposing a first divide-by-2 ILFD design with continuous tuning. In order to design a wide LR, low power consumption ILFD, the impacts of various alternatives of low/high Q tank and injection scheme are deeply analysed, since the ILFD locking range depends on the Q of the tank and injection efficiency. The proposed 3-bit dual-mixing 60 GHz divide-by-2 LC-ILFD is designed with an accumulation of switching varactors binary scaled to compensate PVT variations. It is integrated in the same die with a 4-bit 60 GHz LC-VCO. The overall circuit is designed to allow measurements of the singles blocks stand-alone and working together. The co-layout is carried on with the EM modelling process of passives devices, parasitics and transmission lines extracted from the layout. The inductors models provided by the foundry are qualified up to 40 GHz, therefore the EM analysis is a must for post-layout simulation. The PVT variations have been simulated before manufacturing and, based on the results achieved, a PLL scheme PVT robust, considering frequency calibration, has been patented. The test chip has been measured in the CEA-Leti (Grenoble) during a stay of one week. The operation principle and the optimization trade-offs among power consumption, and locking ranges of the final selected ILFD topology have been demonstrated. Even if the experimental results are not completely in agreement with the simulations, due to modelling error and inaccuracy, the proposed technique has been validated with post-measurement simulations. As demonstrated, the locking range of a low-power, discrete tuned divide-by-2 ILFD can be enhanced by increasing the injection efficiency, without the drawbacks of higher power consumption and chip area. A 4-bits wide tuning range LC-VCO for mm-W applications has been co-designed using the selected 65 nm CMOS process.Postprint (published version
Dynamic and Static Calibration of Ultra-Low-Voltage, Digital-Based Operational Transconductance Amplifiers
The calibration of the effects of process variations and device mismatch in Ultra Low Voltage (ULV) Digital-Based Operational Transconductance Amplifiers (DB-OTAs) is addressed in this paper. For this purpose, two dynamic calibration techniques, intended to dynamically vary the effective strength of critical gates by different modulation strategies, i.e., Digital Pulse Width Modulation (DPWM) and Dyadic Digital Pulse Modulation (DDPM), are explored and compared to classic static calibration. The effectiveness of the calibration approaches as a mean to recover acceptable performance in non-functional samples is verified by Monte-Carlo (MC) post-layout simulations performed on a 300 mV power supply, nW-power DB-OTA in 180 nm CMOS. Based on the same MC post-layout simulations, the impact of each calibration strategy on silicon area, power consumption, and OTA performance is discussed
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A self-calibrated, reconfigurable RF LNA
Modern wireless System-on-Chips (SoCs), such as mobile handsets, sensor networks, and mm-wave systems, integrate an entire RF system on a single CMOS chip. Such highly complex systems require significant on-chip digital signal processing to help improve the performance of highly sensitive analog/RF components. The IC
market being competitive, the ability to achieve first pass silicon success is crucial, due to very high processing and testing time cost. Unfortunately, the ability to achieve first-pass silicon success is becoming increasingly more difficult, due to higher system complexity, higher frequency of operation, increased performance requirements, and higher process skews.
This thesis presents a 2.4 GHz, reconfigurable RF Low Noise Amplifier (LNA) using on-chip peak detection and calibration, to mitigate the deleterious effects of process, voltage and temperature (PVT) variations. The LNA can reconfigure its
input impedance matching, as well as its gain. On-chip detection of optimal input/output impedance matching is performed using an amplitude peak detector. A low power, robust maximum peak point calibration scheme is proposed that calibrates the LNA to the resonant frequency of interest. Measurement results show
that the calibration of the LNA improves the input matching (Sââ) by a maximum of 5 dB , and power gain (Sââ) by 3dB, while not significantly degrading the Noise Figure (NF)
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