Mechanics of Non Planar Interfaces in Flip-Chip Interconnects

With the continued proliferation of low cost, portable consumer electronic products with greater functionality, there is increasing demand for electronic packaging that is smaller, lighter and less expensive. Flip chip is an essential enabling technology for these products. The electrical connection between the chip I/O and substrate is achieved using conductive materials, such as solder, conductive epoxy, metallurgy bump (e.g., gold) and anisotropic conductive adhesives. The interconnect regions of flip-chip packages consists of highly dissimilar materials to meet their functional requirements. The mismatches in properties, contact morphology and crystal orientation at those material interfaces make them vulnerable to failure through delamination and crack growth under various loading patterns. This study encompasses contact between deformable bodies, bonding at the asperities and fracture properties at interfaces formed by the interconnects of flip-chip packages. This is achieved through experimentation and modeling at different length scales, to be able to capture the detailed microstructural features and contact mechanics at interfaces typically found in electronic systems

Evaluation of Anisotropic Conductive Films Based on Vertical Fibers for Post-CMOS Wafer-Level Packaging

In this paper, we investigate the mechanical and electrical properties of an anisotropic conductive film (ACF) on the basis of high-density vertical fibers for a wafer-level packaging (WLP) application. As part of the WaferBoard, a\ud reconfigurable circuit platform for rapid system prototyping,\ud ACF is used as an intermediate film providing compliant and\ud vertical electrical connection between chip contacts and a top surface of an active wafer-size large-area IC. The chosen ACF is first tested by an indentation technique. The results show that the elastic–plastic deformation mode as well as the Young’s modulus and the hardness depend on the indentation depth. Second, the efficiency of the electrical contact is tested using a uniaxial compression on a stack comprising a dummy ball grid array (BGA) board, an ACF, and a thin Al film. For three bump diameters, as the compression increases, the resistance values decrease before reaching low and stable values. Despite the BGA solder bumps exhibit plastic deformation after compression, no damage is found on the ACF film. These results show that vertical fiber ACFs can be used for nonpermanent bonding in a WLP application

Reliability analysis of foil substrate based integration of silicon chips

Flexible electronics has attracted significant attention in the recent past due to the booming wearables market in addition to the ever-increasing interest for faster, thinner and foldable mobile phones. Ultra-thin bare silicon ICs fabricated by thinning down standard ICs to thickness below 50 μm are flexible and therefore they can be integrated on or in polymer foils to create flexible hybrid electronic (FHE) components that could be used to replace rigid standard surface mount device (SMD) components. The fabricated FHE components referred as chip foil packages (CFPs) in this work are ideal candidates for FHE system integration owing to their ability to deliver high performance at low power consumption while being mechanically flexible. However, very limited information is available in the literature regarding the reliability of CFPs under static and dynamic bending. The lack of such vital information is a major obstacle impeding their commercialization. With the aim of addressing this issue, this thesis investigates the static and dynamic bending reliability of CFPs. In this scope, the static bending reliability of CFPs has been investigated in this thesis using flexural bending tests by measuring their fracture strength. Then, Finite Element Method (FEM) simulations have been implemented to calculate the fracture stress of ultra-thin flexible silicon chips where analytical formulas may not be applied. After calculating the fracture stress from FEM simulations, the enhancement in robustness of ultra-thin chips (UTCs) against external load has also been proved and quantified with further experimental investigations. Besides, FEM simulations have also been used to analyse the effect of Young’s Modulus of embedding materials on the robustness of the embedded UTCs. Furthermore, embedding the UTCs in polymer layers has also been experimentally proven to be an effective solution to reduce the influence of thinning and dicing induced damages on the robustness of the embedded UTCs. Traditional interconnection techniques such as wire bonding may not be implemented to interconnect ultra-thin silicon ICs owing to the high mechanical forces involved in the processes that would crack the chips. Therefore, two novel interconnection methods namely (i) flip-chip bonding with Anisotropic Conductive Adhesive (ACA) and (ii) face-up direct metal interconnection have been implemented in this thesis to interconnect ultra-thin silicon ICs to the corresponding interposer patterns on foil substrates. The CFP samples thus fabricated were then used for the dynamic bending reliability investigations. A custom-built test equipment was developed to facilitate the dynamic bending reliability investigations of CFPs. Experimental investigations revealed that the failure of CFPs under dynamic bending was caused mainly by the cracking of the redistribution layer (RDL) interconnecting the chip and the foil. Furthermore, it has also been shown that the CFPs are more vulnerable to repeated compressive bending than to repeated tensile bending. Then, the influence of dimensional factors such as the thickness of the chip as well as the RDL on the dynamic bending reliability of CFPs have also been studied. Upon identifying the plausible cause behind the cracking of the RDL leading to the failure of the CFPs, two methods to improve the dynamic bending reliability of the RDL have been suggested and demonstrated with experimental investigations. The experimental investigations presented in this thesis adds some essential information to the state-of-the-art concerning the static and the dynamic bending reliability of UTCs integrated in polymer foils that are not yet available in the literature and aids to establish in-depth knowledge of mechanical reliability of the components required for manufacturing future FHE systems. The strategies devised to enhance the robustness of UTCs and CFPs could serve as guidelines for fabricating reliable FHE components and systems

Ultra thin ultrafine-pitch chip-package interconnections for embedded chip last approach

Ever growing demands for portability and functionality have always governed the electronic technology innovations. IC downscaling with Moore s law and system miniaturization with System-On-Package (SOP) paradigm has resulted and will continue to result in ultraminiaturized systems with unprecedented functionality at reduced cost. The trend towards 3D silicon system integration is expected to downscale IC I/O pad pitches from 40µm to 1- 5 µm in future. Device- to- system board interconnections are typically accomplished today with either wire bonding or solders. Both of these are incremental and run into either electrical or mechanical barriers as they are extended to higher density of interconnections. Alternate interconnection approaches such as compliant interconnects typically require lengthy connections and are therefore limited in terms of electrical properties, although expected to meet the mechanical requirements. As supply currents will increase upto 220 A by 2012, the current density will exceed the maximum allowable current density of solders. The intrinsic delay and electromigration in solders are other daunting issues that become critical at nanometer size technology nodes. In addition, formation of intermetallics is also a bottleneck that poses significant mechanical issues. Recently, many research groups have investigated various techniques for copper-copper direct bonding. Typically, bonding is carried out at 400oC for 30 min followed by annealing for 30 min. High thermal budget in such process makes it less attractive for integrated systems because of the associated process incompatibilities. In the present study, copper-copper bonding at ultra fine-pitch using advanced nano-conductive and non-conductive adhesives is evaluated. The proposed copper-copper based interconnects using advanced conductive and non-conductive adhesives will be a new fundamental and comprehensive paradigm to solve all the four barriers: 1) I/O pitch 2) Electrical performance 3) Reliability and 4) Cost. This thesis investigates the mechanical integrity and reliability of copper-copper bonding using advanced adhesives through test vehicle fabrication and reliability testing. Test vehicles were fabricated using low cost electro-deposition techniques and assembled onto glass carrier. Experimental results show that proposed copper-copper bonding using advanced adhesives could potentially meet all the system performance requirements for the emerging micro/nano-systems.M.S.Committee Chair: Prof. Rao R Tummala; Committee Member: Dr. Jack Moon; Committee Member: Dr. P M Ra

Performance and Reliability of Polymer-based Sensor Packages at High Temperatures

Electronics is increasingly used in many applications. In addition to new consumer electronics, there is a trend to implement electronics and sensors in many industrial applications, which often requires improved reliability in very demanding conditions. This thesis concerns the effect of high temperature on electronics packages. High temperature tends to accelerate chemical reactions, aging of materials and thereby also failures. Properties of polymer materials, which are often used in electronic packaging, are heavily temperature-dependent. They are, however, very versatile and compatible materials which are readily available and easy to manufacture compared to expensive high-temperature speciality materials such as ceramics. Therefore, using polymers at high temperatures would be highly beneficial. However, it is crucial to understand the effects of high temperature on polymer materials before they are used.This work concentrates on the reliability of polymer-based sensor packages at high temperatures and the changes occurring in their materials at different temperatures. The structures were aged using several high temperature tests including thermal cycling, step stress and thermal storage tests at several temperatures around 200°C. The effects of high temperature on several commercial polymer-based printed circuit boards (PCB) and electrically conductive adhesives (ECA) were analysed from an electrical and mechanical perspective. Moreover, changes in material parameters due to aging were studied to achieve a more profound understanding of the effects of high temperatures.The temperature of 180°C seemed to be low enough not to cause reliability problems in the polymer-based packages studied. Additionally, a good performance in thermal cycling testing up to 180°C was achieved. At 200°C degradation was seen on the surfaces of the polymer materials and their mechanical properties gradually declined. Good electrical performance was nevertheless achieved with suitable material choices. A temperature of 240°C was shown to be too high for extended exposure of the materials studied. With careful material choices relatively good electrical performance was achieved, but FTIR showed dramatic and rapid degradation with most of the polymerbased materials at this temperature. The degradation was much more severe than at 200°C, and the mechanical properties also showed drastic impairment at 240°C.Material selection was shown to be absolutely critical for the reliability of the whole polymer-based package. With poor PCB material interconnections failed much earlier than with more stable PCB materials. Additionally, ECA selection was also important. This thesis showed that polymer-based electronic packages can withstand high temperatures, especially for limited exposure times. However, it is crucial that all materials present are able to withstand the selected temperatures.<br/

Nanowires for 3d silicon interconnection – low temperature compliant nanowire-polymer film for z-axis interconnect

Semiconductor chip packaging has evolved from single chip packaging to 3D heterogeneous system integration using multichip stacking in a single module. One of the key challenges in 3D integration is the high density interconnects that need to be formed between the chips with through-silicon-vias (TSVs) and inter-chip interconnects. Anisotropic Conductive Film (ACF) technology is one of the low-temperature, fine-pitch interconnect method, which has been considered as a potential replacement for solder interconnects in line with continuous scaling of the interconnects in the IC industry. However, the conventional ACF materials are facing challenges to accommodate the reduced pad and pitch size due to the micro-size particles and the particle agglomeration issue. A new interconnect material - Nanowire Anisotropic Conductive Film (NW-ACF), composed of high density copper nanowires of ~ 200 nm diameter and 10-30 µm length that are vertically distributed in a polymeric template, is developed in this work to tackle the constrains of the conventional ACFs and serves as an inter-chip interconnect solution for potential three-dimensional (3D) applications

Silkkipainetuille johtimille toteutetun flip-chip-liitoksen taivutettavuus

The world is heading towards the IoE (Internet of Everything) where everything will be connected to each other. New flexible, light-weight and low-cost electronic devices are needed to add intelligence everywhere in our surroundings. Conventional silicon-based manufacturing is not the best solution because silicon is mechanically rigid and expensive. One way to manufacture these devices cost-effectively in a very large scale is by roll-to-roll screen printing on flexible substrates. However, due to the low calculation performance of current printed electronics, silicon ICs are still needed to act as brains of the devices. Many studies about chip-on-flex or chip-on-film (COF) attachments are available but information about the integration of a silicon chip directly on a screen printed substrate is needed. This thesis investigates bare chip attachment on printed flexible circuitry and evaluates its subsequent level of bendability. The chip was attached on the high-density rotary screen printed circuitry using a flip-chip technique with anisotropic conductive adhesives (ACP and ACF). A selection of chips was stud bumped with gold. Chips without bumps were more challenging to bond due to the surface roughness of the screen printed lines and a small marginal of the suitable bonding pressure. A chip should be exactly parallel with the substrate while bonding so that the pressure is correct on all pads. After finding the suitable bonding parameters, approximately 90 % of the ACP bonded and 96 % of the ACF bonded interconnections worked without bumps. Stud bumping increased the yield almost to 100 % and decreased the contact resistances approximately 75% making the contacts more reliable. Calendering was tested for printed lines to increase their uniformity and decrease the pad height deviation by heating and pressing them with high force. Calendering reduced the line heights by approximately 1 μm and decreased the surface roughness, but following this process there still existed at least a 2 μm variation in the line heights (nominal line height 5 μm). Bending reliability of the chip attachments on flexible plastic substrates was determined using a self-built bending test set-up which bends the sample between two rigid plates. All chip attachments studied withstood at least a 2.5 cm bending radius. The main results of this thesis were to demonstrate bare die integration on screen printed circuitry and to show its suitability for flexible hybrid electronic applications. Still further development of the bonding process and materials are needed to achieve more reliable long-term solutions

Development and reliability of a direct access sensor using flip chip on flex technology with anisotropic conductive adhesive

Technological developments in biomedical microsystems are opening up new opportunities to improve healthcare procedures. Swallowable diagnostic sensing capsules are an example of these. In none of the diagnostic sensing capsules, is the sensor’s first level packaging achieved via Flip Chip Over Hole (FCOH) method using Anisotropic Conductive Adhesive (ACA). In a capsule application with direct access sensor (DAS), ACA not only provides the electrical interconnection but simultaneously seals the interconnect area and the underlying electronics. The development showed that the ACA FCOH was a viable option for the DAS interconnection. Adequate adhesive formed a strong joint that withstood a shear stress of 120N/mm2 and a compressive stress of 6N required to secure the final sensor assembly in place before encapsulation. Electrical characterization of the ACA joint in a fluid environment showed that the ACA was saturated with moisture and that the ions in the solution actively contributed to the leakage current, characterized by the varying rate of change of conductance. Long term hygrothermal aging of the ACA joint showed that a thermal strain of 0.004 and a hygroscopic strain of 0.0052 were present and resulted in a fatigue like process. In-vitro tests showed that high temperature and acidity had a deleterious effect of the ACA and its joint. It also showed that the ACA contact joints positioned at around or over 1mm would survive the gastrointestinal (GI) fluids and would be able to provide a reliable contact during the entire 72hr of the GI transit time. A final capsule demonstrator was achieved by successfully integrating the DAS, the battery and the final foldable circuitry into a glycerine capsule. Final capsule soak tests suggested that the silicone encapsulated system could survive the 72hr gut transition

Novel fine pitch interconnection methods using metallised polymer spheres

There is an ongoing demand for electronics devices with more functionality while reducing size and cost, for example smart phones and tablet personal computers. This requirement has led to significantly higher integrated circuit input/output densities and therefore the need for off-chip interconnection pitch reduction. Flip-chip processes utilising anisotropic conductive adhesives anisotropic conductive films (ACAs/ACFs) have been successfully applied in liquid crystal display (LCD) interconnection for more than two decades. However the conflict between the need for a high particle density, to ensure sufficient the conductivity, without increasing the probability of short circuits has remained an issue since the initial utilization of ACAs/ACFs for interconnection. But this issue has become even more severe with the challenge of ultra-fine pitch interconnection. This thesis advances a potential solution to this challenge where the conductive particles typically used in ACAs are selectively deposited onto the connections ensuring conductivity without bridging. The research presented in this thesis work has been undertaken to advance the fundamental understanding of the mechanical characteristics of micro-sized metal coated polymer particles (MCPs) and their application in fine or ultra-fine pitch interconnections. This included use of a new technique based on an in-situ nanomechanical system within SEM which was utilised to study MCP fracture and failure when undergoing deformation. Different loading conditions were applied to both uncoated polymer particles and MCPs, and the in-situ system enables their observation throughout compression. The results showed that both the polymer particles and MCP display viscoelastic characteristics with clear strain-rate hardening behaviour, and that the rate of compression therefore influences the initiation of cracks and their propagation direction. Selective particle deposition using electrophoretic deposition (EPD) and magnetic deposition (MD) of Ni/Au-MCPs have been evaluated and a fine or ultra-fine pitch deposition has been demonstrated, followed by a subsequent assembly process. The MCPs were successfully positively charged using metal cations and this charging mechanism was analysed. A new theory has been proposed to explain the assembly mechanism of EPD of Ni/Au coated particles using this metal cation based charging method. The magnetic deposition experiments showed that sufficient magnetostatic interaction force between the magnetized particles and pads enables a highly selective dense deposition of particles. Successful bonding to form conductive interconnections with pre-deposited particles have been demonstrated using a thermocompression flip-chip bonder, which illustrates the applicable capability of EPD of MCPs for fine or ultra-fine pitch interconnection