The road to fully integrated DC-DC conversion via the switched-capacitor approach

This paper provides a perspective on progress toward realization of efficient, fully integrated dc-dc conversion and regulation functionality in CMOS platforms. In providing a comparative assessment between the inductor-based and switched-capacitor approaches, the presentation reviews the salient features in effectiveness in utilization of switch technology and in use and implementation of passives. The analytical conclusions point toward the strong advantages of the switched-capacitor (SC) approach with respect to both switch utilization and much higher energy densities of capacitors versus inductors. The analysis is substantiated with a review of recently developed and published integrated dc-dc converters of both the inductor-based and SC types. © 2012 IEEE

One-cycle control of switching converters

A new large-signal nonlinear control technique is proposed to control the duty-ratio d of a switch such that in each cycle the average value of a switched variable of the switching converter is exactly equal to or proportional to the control reference in the steady-state or in a transient. One-cycle control rejects power source perturbations in one switching cycle; the average value of the switched variable follows the dynamic reference in one switching cycle; and the controller corrects switching errors in one switching cycle. There is no steady-state error nor dynamic error between the control reference and the average value of the switched variable. Experiments with a constant frequency buck converter have demonstrated the robustness of the control method and verified the theoretical predictions. This new control method is very general and applicable to all types of pulse-width-modulated, resonant-based, or soft-switched switching converters for either voltage or current control in continuous or discontinuous conduction mode. Furthermore, it can be used to control any physical variable or abstract signal that is in the form of a switched variable or can be converted to the form of a switched variable

ASDTIC control and standardized interface circuits applied to buck, parallel and buck-boost dc to dc power converters

Versatile standardized pulse modulation nondissipatively regulated control signal processing circuits were applied to three most commonly used dc to dc power converter configurations: (1) the series switching buck-regulator, (2) the pulse modulated parallel inverter, and (3) the buck-boost converter. The unique control concept and the commonality of control functions for all switching regulators have resulted in improved static and dynamic performance and control circuit standardization. New power-circuit technology was also applied to enhance reliability and to achieve optimum weight and efficiency

A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC-DC Converters in 28 nm FDSOI

This work demonstrates a RISC-V vector microprocessor implemented in 28 nm FDSOI with fully integrated simultaneous-switching switched-capacitor DC-DC (SC DC-DC) converters and adaptive clocking that generates four on-chip voltages between 0.45 and 1 V using only 1.0 V core and 1.8 V IO voltage inputs. The converters achieve high efficiency at the system level by switching simultaneously to avoid charge-sharing losses and by using an adaptive clock to maximize performance for the resulting voltage ripple. Details about the implementation of the DC-DC switches, DC-DC controller, and adaptive clock are provided, and the sources of conversion loss are analyzed based on measured results. This system pushes the capabilities of dynamic voltage scaling by enabling fast transitions (20 ns), simple packaging (no off-chip passives), low area overhead (16%), high conversion efficiency (80%-86%), and high energy efficiency (26.2 DP GFLOPS/W) for mobile devices

Morphing Switched-Capacitor Converters with Variable Conversion Ratio

High-voltage-gain and wide-input-range dc-dc converters are widely used in various electronics and industrial products such as portable devices, telecommunication, automotive, and aerospace systems. The two-stage converter is a widely adopted architecture for such applications, and it is proven to have a higher efficiency as compared with that of the single-stage converter. This paper presents a modular-cell-based morphing switched-capacitor (SC) converter for application as a front-end converter of the two-stage converter. The conversion ratio of this converter is flexible and variable and can be freely extended by increasing more SC modules. The varying conversion ratio is achieved through the morphing of the converter's structure corresponding to the amplitude of the input voltage. This converter is light and compact, and is highly efficient over a very wide range of input voltage and load conditions. Experimental work on a 25-W, 6-30-V input, 3.5-8.5-V output prototype, is performed. For a single SC module, the efficiency over the entire input voltage range is higher than 98%. Applied into the two-stage converter, the overall efficiency achievable over the entire operating range is 80% including the driver's loss

Asynchronous Circuit Stacking for Simplified Power Management

As digital integrated circuits (ICs) continue to increase in complexity, new challenges arise for designers. Complex ICs are often designed by incorporating multiple power domains therefore requiring multiple voltage converters to produce the corresponding supply voltages. These converters not only take substantial on-chip layout area and/or off-chip space, but also aggregate the power loss during the voltage conversions that must occur fast enough to maintain the necessary power supplies. This dissertation work presents an asynchronous Multi-Threshold NULL Convention Logic (MTNCL) “stacked” circuit architecture that alleviates this problem by reducing the number of voltage converters needed to supply the voltage the ICs operate at. By stacking multiple MTNCL circuits between power and ground, supplying a multiple of VDD to the entire stack and incorporating simple control mechanisms, the dynamic range fluctuation problem can be mitigated. A 130nm Bulk CMOS process and a 32nm Silicon-on-Insulator (SOI) CMOS process are used to evaluate the theoretical effect of stacking different circuitry while running different workloads. Post parasitic physical implementations are then carried out in the 32nm SOI process for demonstrating the feasibility and analyzing the advantages of the proposed MTNCL stacking architecture

Experimental Test bed to De-Risk the Navy Advanced Development Model

This paper presents a reduced scale demonstration test-bed at the University of Texas’ Center for Electromechanics (UT-CEM) which is well equipped to support the development and assessment of the anticipated Navy Advanced Development Model (ADM). The subscale ADM test bed builds on collaborative power management experiments conducted as part of the Swampworks Program under the US/UK Project Arrangement as well as non-military applications. The system includes the required variety of sources, loads, and controllers as well as an Opal-RT digital simulator. The test bed architecture is described and the range of investigations that can be carried out on it is highlighted; results of preliminary system simulations and some initial tests are also provided. Subscale ADM experiments conducted on the UT-CEM microgrid can be an important step in the realization of a full-voltage, full-power ADM three-zone demonstrator, providing a test-bed for components, subsystems, controls, and the overall performance of the Medium Voltage Direct Current (MVDC) ship architecture.Center for Electromechanic