Towards Physical Hybrid Systems

Some hybrid systems models are unsafe for mathematically correct but physically unrealistic reasons. For example, mathematical models can classify a system as being unsafe on a set that is too small to have physical importance. In particular, differences in measure zero sets in models of cyber-physical systems (CPS) have significant mathematical impact on the mathematical safety of these models even though differences on measure zero sets have no tangible physical effect in a real system. We develop the concept of "physical hybrid systems" (PHS) to help reunite mathematical models with physical reality. We modify a hybrid systems logic (differential temporal dynamic logic) by adding a first-class operator to elide distinctions on measure zero sets of time within CPS models. This approach facilitates modeling since it admits the verification of a wider class of models, including some physically realistic models that would otherwise be classified as mathematically unsafe. We also develop a proof calculus to help with the verification of PHS.Comment: CADE 201

Chain models, trees of singular cardinality and dynamic EF games

Let κ be a singular cardinal. Karp's notion of a chain model of size ? is defined to be an ordinary model of size κ along with a decomposition of it into an increasing union of length cf(κ). With a notion of satisfaction and (chain)-isomorphism such models give an infinitary logic largely mimicking first order logic. In this paper we associate to this logic a notion of a dynamic EF-game which gauges when two chain models are chain-isomorphic. To this game is associated a tree which is a tree of size κ with no κ-branches (even no cf(κ)-branches). The measure of how non-isomorphic the models are is reflected by a certain order on these trees, called reduction. We study the collection of trees of size κ with no κ-branches under this notion and prove that when cf(κ) = ω this collection is rather regular; in particular it has universality number exactly κ+. Such trees are then used to develop a descriptive set theory of the space cf(κ)κ.The main result of the paper gives in the case of κ strong limit singular an exact connection between the descriptive set-theoretic complexity of the chain isomorphism orbit of a model, the reduction order on the trees and winning strategies in the corresponding dynamic EF games. In particular we obtain a neat analog of the notion of Scott watershed from the Scott analysis of countable models

Current Comparison Domino based CHSK Domino Logic Technique for Rapid Progression and Low Power Alleviation

The proposed domino logic is developed with the combination of Current Comparison Domino (CCD) logic and Conditional High Speed Keeper (CHSK) domino logic. In order to improve the performance metrics like power, delay and noise immunity, the redesign of CHSK is proposed with the CCD. The performance improvement is based on the parasitic capacitance, which reduces on the dynamic node for robust and rapid process of the circuit. The proposed domino logic is designed with keeper and without keeper to measure the performance metrics of the circuit. The outcomes of the proposed domino logic are better when compared to the existing domino logic circuits. The simulation of the proposed CHSK based on the CCD logic circuit is carried out in Cadence Virtuoso tool

Interaction Graphs: Full Linear Logic

Interaction graphs were introduced as a general, uniform, construction of dynamic models of linear logic, encompassing all Geometry of Interaction (GoI) constructions introduced so far. This series of work was inspired from Girard's hyperfinite GoI, and develops a quantitative approach that should be understood as a dynamic version of weighted relational models. Until now, the interaction graphs framework has been shown to deal with exponentials for the constrained system ELL (Elementary Linear Logic) while keeping its quantitative aspect. Adapting older constructions by Girard, one can clearly define "full" exponentials, but at the cost of these quantitative features. We show here that allowing interpretations of proofs to use continuous (yet finite in a measure-theoretic sense) sets of states, as opposed to earlier Interaction Graphs constructions were these sets of states were discrete (and finite), provides a model for full linear logic with second order quantification

New Concepts Towards the Synthesis of Digital Circuits Through Genetic Algorithms

This paper analyses the performance of a Genetic Algorithm using two new concepts, namely a static fitness function including a discontinuity measure and a fractional-order dynamic fitness function, for the synthesis of combinational logic circuits. In both cases, experiments reveal superior results in terms of speed and convergence to achieve a solution

Digital Circuit Design Using Dynamic Fitness Functions

This paper proposes and analyses the performance of a Genetic Algorithm using two new concepts, namely a static fitness function including a discontinuity measure and a fractional-order dynamic fitness function, for the synthesis of combinational logic circuits. In both cases, experiments reveal superior results in terms of speed and convergence to achieve a solution.N/

Fractional Dynamic Fitness Functions for GA-based Circuit Design

This paper proposes and analyses the performance of a Genetic Algorithm (GA) using two new concepts, namely a static fitness function including a discontinuity measure and a fractional-order dynamic fitness function. The GA is adopted for the synthesis of combinational logic circuits. In both cases, experiments reveal superior results in terms of speed and convergence to achieve a solution.N/

IMPLEMENTATION HIGH POWER EFFICIENCY AND FLEXIBLE CHARGE RECYCLING USING DYNAMIC CIRCUIT TECHNIQUE

In computer circuit style, dynamic logic could be a style methodology in combinatory logic circuits, particularly those enforced in MOS technology. Dynamic circuits square measure wide employed in order to unravel the problems occurred within the information path and therefore the essential components of the microchip. The power consumption is considerably in dynamic circuits thanks to their shift activity. So as to get high-performance dynamic circuits square measure employed in microprocessors as a result of their special options such as speed and space. during this paper, we have a tendency to planned versatile charge utilization style methodology and dynamic circuit choice rule so as to attain high efficiency within the information path. Per the planned methodology the simulation results of the planning show the consumption of the ALU (Arithmetic and Logic Unit) with planned technique is reduced considerably compared to the standard ALU