Dynamic calibration of current-steering DAC

The demand for high-speed communication systems has dramatically increased during the last decades. Working as an interface between the digital and analog world, Digital-to-Analog converters (DACs) are becoming more and more important because they are a key part which limits the accuracy and speed of an overall system. Consequently, the requirements for high-speed and high-accuracy DACs are increasingly demanding. It is well recognized that dynamic performance of the DACs degrades dramatically with increasing input signal frequencies and update rates. The dynamic performance is often characterized by the spurious free dynamic range (SFDR). The SFDR is determined by the spectral harmonics, which are attributable to system nonlinearities.;A new calibration approach is presented in this thesis that compensates for the dynamic errors in performance. In this approach, the nonlinear components of the input dependent and previous input code dependent errors are characterized, and correction codes that can be used to calibrate the DAC for these nonlinearities are stored in a two-dimensional error look-up table. A series of pulses is generated at run time by addressing the error look-up table with the most significant bits of the Boolean input and by using the corresponding output to drive a calibration DAC whose output is summed with the original DAC output. The approach is applied at both the behavioral level and the circuit level in current-steering DAC.;The validity of this approach is verified by simulation. These simulations show that the dynamic nonlinearities can be dramatically reduced with this calibration scheme. The simulation results also show that this calibration approach is robust to errors in both the width and height of calibration pulses.;Experimental measurement results are also provided for a special case of this dynamic calibration algorithm that show that the dynamic performance can be improved through dynamic calibration, provided the mean error values in the table are close to their real values

A 14b 200MS/s DAC with SFDR>78dBc, IM3

A 14-bit 200MS/s current-steering DAC with a novel digital calibration technique called dynamic-mismatch mapping (DMM) is presented. Compared to traditional static-mismatch mapping and dynamic element matching, DMM reduces the nonlinearities caused by both amplitude and timing errors, without noise penalty. This 0.14µm CMOS DAC achieves a state-of-the-art performance of SFDR>78dBc, IM

Smart and high-performance digital-to-analog converters with dynamic-mismatch mapping

The trends of advanced communication systems, such as the high data rate in multi-channel base-stations and digital IF conversion in software-defined radios, have caused a continuously increasing demand for high performance interface circuits between the analog and the digital domain. A Digital-to-Analog converter (DAC) is such an interface circuit in the transmitter path. High bandwidth, high linearity and low noise are the main design challenges in high performance DACs. Current-steering is the most suitable architecture to meet these performance requirements. The aim of this thesis is to develop design techniques for high-speed high-performance Nyquist current-steering DACs, especially for the design of DACs with high dynamic performance, e.g. high linearity and low noise. The thesis starts with an introduction to DACs in chapter 2. The function in time/frequency domain, performance specifications, architectures and physical implementations of DACs are brie y discussed. Benchmarks of state-of-the-art published Nyquist DACs are also given. Chapter 3 analyzes performance limitations by various error sources in Nyquist current-steering DACs. The outcome shows that in the frequency range of DC to hundreds of MHz, mismatch errors, i.e. amplitude and timing errors, dominate the DAC linearity. Moreover, as frequencies increase, the effect of timing errors becomes more and more dominant over that of amplitude errors. Two new parameters, i.e. dynamic-INL and dynamic-DNL, are proposed to evaluate the matching of current cells. Compared to the traditional static-INL/DNL, the dynamic-INL/DNL can describe the matching between current cells more accurately and completely. By reducing the dynamic-INL/DNL, the non-linearities caused by all mismatch errors can be reduced. Therefore, both the DAC static and dynamic performance can be improved. The dynamic-INL/DNL are frequency-dependent parameters based on the measurement modulation frequency fm. This fm determines the weight between amplitude and timing errors in the dynamic-INL/DNL. Actually, this gives a freedom to optimize the DAC performance for different applications, e.g. low fm for low frequency applications and high fm for high frequency applications. Chapter 4 summarizes the existing design techniques for intrinsic and smart DACs. Due to technology limitations, it is diffcult to reduce the mismatch errors just by intrinsic DAC design with reasonable chip area and power consumption. Therefore, calibration techniques are required. An intrinsic DAC with calibration is called a smart DAC. Existing analog calibration techniques mainly focus on current source calibration, so that the amplitude error can be reduced. Dynamic element matching is a kind of digital calibration technique. It can reduce the non-linearities caused by all mismatch errors, but at the cost of an increased noise oor. Mapping is another kind of digital calibration technique and will not increase the noise. Mapping, as a highly digitized calibration technique, has many advantages. Since it corrects the error effects in the digital domain, the DAC analog core can be made clean and compact, which reduces the parasitics and the interference generated in the analog part. Traditional mapping is static-mismatch mapping, i.e. mapping only for amplitude errors, which many publications have already addressed on. Several concepts have also been proposed on mapping for timing errors. However, just mapping for amplitude or timing error is not enough to guarantee a good performance. This work focuses on developing mapping techniques which can correct both amplitude and timing errors at the same time. Chapter 5 introduces a novel mapping technique, called dynamic-mismatch mapping (DMM). By modulating current cells as square-wave outputs and measuring the dynamic-mismatch errors as vectors, DMM optimizes the switching sequence of current cells based on dynamic-mismatch error cancelation such that the dynamic-INL can be reduced. After reducing the dynamic-INL, the non-linearities caused by both amplitude and timing errors can be significantly reduced in the whole Nyquist band, which is confirmed by Matlab behavioral-level Monte-Carlo simulations. Compared to traditional static-mismatch mapping (SMM), DMM can reduce the non-linearities caused by both amplitude and timing errors. Compared to dynamic element matching (DEM), DMM does not increase the noise floor. The dynamic-mismatch error has to be accurately measured in order to gain the maximal benefit from DMM. An on-chip dynamic-mismatch error sensor based on a zero-IF receiver is proposed in chapter 6. This sensor is especially designed for low 1/f noise since the signal is directly down-converted to DC. Its signal transfer function and noise analysis are also given and con??rmed by transistor-level simulations. Chapter 7 gives a design example of a 14-bit current-steering DAC in 0.14mum CMOS technology. The DAC can be configured in an intrinsic-DAC mode or a smart-DAC mode. In the intrinsic-DAC mode, the 14-bit 650MS/s intrinsic DAC core achieves a performance of SFDR>65dBc across the whole 325MHz Nyquist band. In the smart-DAC mode, compared to the intrinsic DAC performance, DMM improves the DAC performance in the whole Nyquist band, providing at least 5dB linearity improvement at 200MS/s and without increasing the noise oor. This 14-bit 200MS/s smart DAC with DMM achieves a performance of SFDR>78dBc, IM

Baseband analog front-end and digital back-end for reconfigurable multi-standard terminals

Multimedia applications are driving wireless network operators to add high-speed data services such as Edge (E-GPRS), WCDMA (UMTS) and WLAN (IEEE 802.11a,b,g) to the existing GSM network. This creates the need for multi-mode cellular handsets that support a wide range of communication standards, each with a different RF frequency, signal bandwidth, modulation scheme etc. This in turn generates several design challenges for the analog and digital building blocks of the physical layer. In addition to the above-mentioned protocols, mobile devices often include Bluetooth, GPS, FM-radio and TV services that can work concurrently with data and voice communication. Multi-mode, multi-band, and multi-standard mobile terminals must satisfy all these different requirements. Sharing and/or switching transceiver building blocks in these handsets is mandatory in order to extend battery life and/or reduce cost. Only adaptive circuits that are able to reconfigure themselves within the handover time can meet the design requirements of a single receiver or transmitter covering all the different standards while ensuring seamless inter-interoperability. This paper presents analog and digital base-band circuits that are able to support GSM (with Edge), WCDMA (UMTS), WLAN and Bluetooth using reconfigurable building blocks. The blocks can trade off power consumption for performance on the fly, depending on the standard to be supported and the required QoS (Quality of Service) leve

Differential temperature sensors: Review of applications in the test and characterization of circuits, usage and design methodology

Differential temperature sensors can be placed in integrated circuits to extract a signature ofthe power dissipated by the adjacent circuit blocks built in the same silicon die. This review paper firstdiscusses the singularity that differential temperature sensors provide with respect to other sensortopologies, with circuit monitoring being their main application. The paper focuses on the monitoringof radio-frequency analog circuits. The strategies to extract the power signature of the monitoredcircuit are reviewed, and a list of application examples in the domain of test and characterizationis provided. As a practical example, we elaborate the design methodology to conceive, step bystep, a differential temperature sensor to monitor the aging degradation in a class-A linear poweramplifier working in the 2.4 GHz Industrial Scientific Medical—ISM—band. It is discussed how,for this particular application, a sensor with a temperature resolution of 0.02 K and a high dynamicrange is required. A circuit solution for this objective is proposed, as well as recommendations for thedimensions and location of the devices that form the temperature sensor. The paper concludes with adescription of a simple procedure to monitor time variability.Postprint (published version

Description of the Spacecraft Control Laboratory Experiment (SCOLE) facility

A laboratory facility for the study of control laws for large flexible spacecraft is described. The facility fulfills the requirements of the Spacecraft Control Laboratory Experiment (SCOLE) design challenge for a laboratory experiment, which will allow slew maneuvers and pointing operations. The structural apparatus is described in detail sufficient for modelling purposes. The sensor and actuator types and characteristics are described so that identification and control algorithms may be designed. The control implementation computer and real-time subroutines are also described