Behavioral Models of I/O Ports from Measured Transient Waveforms

This paper addresses the development of accurate and efficient behavioral models of digital integrated circuit ports from measured transient responses. The proposed approach is based on the estimation of parametric models from port voltage and current waveforms. The modeling process is described and applied to the modeling of output ports. Its feasibility is demonstrated by the identification of a real device from actual measurements, and by the comparison of the predicted device response with the measured one

PMU-Based ROCOF Measurements: Uncertainty Limits and Metrological Significance in Power System Applications

In modern power systems, the Rate-of-Change-of-Frequency (ROCOF) may be largely employed in Wide Area Monitoring, Protection and Control (WAMPAC) applications. However, a standard approach towards ROCOF measurements is still missing. In this paper, we investigate the feasibility of Phasor Measurement Units (PMUs) deployment in ROCOF-based applications, with a specific focus on Under-Frequency Load-Shedding (UFLS). For this analysis, we select three state-of-the-art window-based synchrophasor estimation algorithms and compare different signal models, ROCOF estimation techniques and window lengths in datasets inspired by real-world acquisitions. In this sense, we are able to carry out a sensitivity analysis of the behavior of a PMU-based UFLS control scheme. Based on the proposed results, PMUs prove to be accurate ROCOF meters, as long as the harmonic and inter-harmonic distortion within the measurement pass-bandwidth is scarce. In the presence of transient events, the synchrophasor model looses its appropriateness as the signal energy spreads over the entire spectrum and cannot be approximated as a sequence of narrow-band components. Finally, we validate the actual feasibility of PMU-based UFLS in a real-time simulated scenario where we compare two different ROCOF estimation techniques with a frequency-based control scheme and we show their impact on the successful grid restoration.Comment: Manuscript IM-18-20133R. Accepted for publication on IEEE Transactions on Instrumentation and Measurement (acceptance date: 9 March 2019

Assessment of unintentional islanding operations in distribution networks with large induction motors

This paper is aimed at assessing the impact of unintentional islanding operations (IOs) in the presence of large induction motors (IMs) within distribution networks (DNs). When a fault occurs,followingthecircuitbreaker(CB)faultclearing,theIMsacttransientlyasgenerators,duetoits inertia, until the CB reclosing takes place. The present work is the outcome of a project carried out in a small DN, where ¿eld measurements were recorded over two years. This paper provides a detailed description of the test system, a selected list of ¿eld measurements, and a discussion on modeling guidelinesusedtocreatethemodeloftheactualpowersystem. Themaingoalistovalidatethesystem model by comparing ¿eld measurements with simulation results. The comparison of simulations and ¿eld measurements prove the appropriateness of the modeling guidelines used in this work and highlight the high accuracy achieved in the implemented three-phase Matlab/Simulink modelPostprint (published version

Gate-level timing analysis and waveform evaluation

Static timing analysis (STA) is an integral part of modern VLSI chip design. Table lookup based methods are widely used in current industry due to its fast runtime and mature algorithms. Conventional STA algorithms based on table-lookup methods are developed under many assumptions in timing analysis; however, most of those assumptions, such as that input signals and output signals can be accurately modeled as ramp waveforms, are no longer satisfactory to meet the increasing demand of accuracy for new technologies. In this dissertation, we discuss several crucial issues that conventional STA has not taken into consideration, and propose new methods to handle these issues and show that new methods produce accurate results. In logic circuits, gates may have multiple inputs and signals can arrive at these inputs at different times and with different waveforms. Different arrival times and waveforms of signals can cause very different responses. However, multiple-input transition effects are totally overlooked by current STA tools. Using a conventional single-input transition model when multiple-input transition happens can cause significant estimation errors in timing analysis. Previous works on this issue focus on developing a complicated gate model to simulate the behavior of logic gates. These methods have high computational cost and have to make significant changes to the prevailing STA tools, and are thus not feasible in practice. This dissertation proposes a simplified gate model, uses transistor connection structures to capture the behavior of multiple-input transitions and requires no change to the current STA tools. Another issue with table lookup based methods is that the load of each gate in technology libraries is modeled as a single lumped capacitor. But in the real circuit, the Abstract 2 gate connects to its subsequent gates via metal wires. As the feature size of integrated circuit scales down, the interconnection cannot be seen as a simple capacitor since the resistive shielding effect will largely affect the equivalent capacitance seen from the gate. As the interconnection has numerous structures, tabulating the timing data for various interconnection structures is not feasible. In this dissertation, by using the concept of equivalent admittance, we reduce an arbitrary interconnection structure into an equivalent π-model RC circuit. Many previous works have mapped the π-model to an effective capacitor, which makes the table lookup based methods useful again. However, a capacitor cannot be equivalent to a π-model circuit, and will thus result in significant inaccuracy in waveform evaluation. In order to obtain an accurate waveform at gate output, a piecewise waveform evaluation method is proposed in this dissertation. Each part of the piecewise waveform is evaluated according to the gate characteristic and load structures. Another contribution of this dissertation research is a proposed equivalent waveform search method. The signal waveforms can be very complicated in the real circuits because of noises, race hazards, etc. The conventional STA only uses one attribute (i.e., transition time) to describe the waveform shape which can cause significant estimation errors. Our approach is to develop heuristic search functions to find equivalent ramps to approximate input waveforms. Here the transition time of a final ramp can be completely different from that of the original waveform, but we can get higher accuracy on output arrival time and transition time. All of the methods mentioned in this dissertation require no changes to the prevailing STA tools, and have been verified across different process technologies

A fast and retargetable framework for logic-IP-internal electromigration assessment comprehending advanced waveform effects

A new methodology for system-on-chip-level logic-IP-internal electromigration verification is presented in this paper, which significantly improves accuracy by comprehending the impact of the parasitic RC loading and voltage-dependent pin capacitance in the library model. It additionally provides an on-the-fly retargeting capability for reliability constraints by allowing arbitrary specifications of lifetimes, temperatures, voltages, and failure rates, as well as interoperability of the IPs across foundries. The characterization part of the methodology is expedited through the intelligent IP-response modeling. The ultimate benefit of the proposed approach is demonstrated on a 28-nm design by providing an on-the-fly specification of retargeted reliability constraints. The results show a high correlation with SPICE and were obtained with an order of magnitude reduction in the verification runtime.Peer ReviewedPostprint (author's final draft

VLSI Design

This book provides some recent advances in design nanometer VLSI chips. The selected topics try to present some open problems and challenges with important topics ranging from design tools, new post-silicon devices, GPU-based parallel computing, emerging 3D integration, and antenna design. The book consists of two parts, with chapters such as: VLSI design for multi-sensor smart systems on a chip, Three-dimensional integrated circuits design for thousand-core processors, Parallel symbolic analysis of large analog circuits on GPU platforms, Algorithms for CAD tools VLSI design, A multilevel memetic algorithm for large SAT-encoded problems, etc

Register-transfer-level power profiling for system-on-chip power distribution network design and signoff

Abstract. This thesis is a study of how register-transfer-level (RTL) power profiling can help the design and signoff of power distribution network in digital integrated circuits. RTL power profiling is a method which collects RTL power estimation results to a single power profile which then can be analysed in order to find interesting time windows for specifying power distribution network design and signoff. The thesis starts with theory part. Complementary metal-oxide semiconductor (CMOS) inverter power dissipation is studied at first. Next, power distribution network structure and voltage drop problems are introduced. Voltage drop is demonstrated by using power distribution network impedance figures. Common on-chip power distribution network structure is introduced, and power distribution network design flow is outlined. Finally, decoupling capacitors function and impact on power distribution network impedance are thoroughly explained. The practical part of the thesis contains RTL power profiling flow details and power profiling flow results for one simulation case in one design block. Also, some methods of improving RTL power estimation accuracy are discussed and calibration with extracted parasitic is then used to get new set of power profiling time windows. After the results are presented, overall RTL power estimation accuracy is analysed and resulted time windows are compared to reference gate-level time windows. RTL power profiling result analysis shows that resulted time windows match the theory and RTL power profiling seems to be a promising method for finding time windows for power distribution network design and signoff.Rekisterisiirtotason tehoprofilointi järjestelmäpiirin tehonsiirtoverkon suunnittelussa ja verifioinnissa. Tiivistelmä. Tässä työssä tutkitaan, miten rekisterisiirtotason (RTL) tehoprofilointi voi auttaa digitaalisten integroitujen piirien tehonsiirtoverkon suunnittelussa ja verifioinnissa. RTL-tehoprofilointi on menetelmä, joka analysoi RTL-tehoestimoinnista saadusta tehokäyrästä hyödyllisiä aikaikkunoita tehonsiirtoverkon suunnitteluun ja verifiointiin. Työ alkaa teoriaosuudella, jonka aluksi selitetään, miten CMOS-invertteri kuluttaa tehoa. Seuravaksi esitellään tehonsiirtoverkon rakenne ja pahimmat tehonsiirtoverkon jännitehäviön aiheuttajat. Jännitehäviötä havainnollistetaan myös piirikaavioiden ja impedanssikäyrien avustuksella. Lisäksi integroidun piirin tehonsiirtoverkon suunnitteluvuo ja yleisin rakenne on esitelty. Lopuksi teoriaosuus käsittelee yksityiskohtaisesti ohituskondensaattoreiden toiminnan ja vaikutuksen tehonsiirtoverkon kokonaisimpedanssiin. Työn kokeellisessa osuudessa esitellään ensin tehoprofiloinnin vuo ja sen jälkeen vuon tulokset yhdelle esimerkkilohkolle yhdessä simulaatioajossa. Lisäksi tässä osiossa käsitellään RTL-tehoestimoinnin tarkkuutta ja tehdään RTL-tehoprofilointi loisimpedansseilla kalibroidulle RTL-mallille. Lopuksi RTL-tehoestimoinnin tuloksia ja saatuja RTL-tehoprofiloinnin aikaikkunoita analysoidaan ja verrataan porttitason mallin tuloksiin. RTL-tehoprofiloinnin tulosten analysointi osoittaa, että saatavat aikaikkunat vastaavat teoriaa ja että RTL-tehoprofilointi näyttää lupaavalta menetelmältä tehosiirtoverkon analysoinnin ja verifioinnin aikaikkunoiden löytämiseen

Monitoring of the central blood pressure waveform via a conformal ultrasonic device.

Continuous monitoring of the central-blood-pressure waveform from deeply embedded vessels, such as the carotid artery and jugular vein, has clinical value for the prediction of all-cause cardiovascular mortality. However, existing non-invasive approaches, including photoplethysmography and tonometry, only enable access to the superficial peripheral vasculature. Although current ultrasonic technologies allow non-invasive deep-tissue observation, unstable coupling with the tissue surface resulting from the bulkiness and rigidity of conventional ultrasound probes introduces usability constraints. Here, we describe the design and operation of an ultrasonic device that is conformal to the skin and capable of capturing blood-pressure waveforms at deeply embedded arterial and venous sites. The wearable device is ultrathin (240 μm) and stretchable (with strains up to 60%), and enables the non-invasive, continuous and accurate monitoring of cardiovascular events from multiple body locations, which should facilitate its use in a variety of clinical environments