24 research outputs found

    Ultra-low Quiescent Current NMOS Low Dropout Regulator With Fast Transient response for Always-On Internet-of-Things Applications

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    abstract: The increased adoption of Internet-of-Things (IoT) for various applications like smart home, industrial automation, connected vehicles, medical instrumentation, etc. has resulted in a large scale distributed network of sensors, accompanied by their power supply regulator modules, control and data transfer circuitry. Depending on the application, the sensor location can be virtually anywhere and therefore they are typically powered by a localized battery. To ensure long battery-life without replacement, the power consumption of the sensor nodes, the supply regulator and, control and data transmission unit, needs to be very low. Reduction in power consumption in the sensor, control and data transmission is typically done by duty-cycled operation such that they are on periodically only for short bursts of time or turn on only based on a trigger event and are otherwise powered down. These approaches reduce their power consumption significantly and therefore the overall system power is dominated by the consumption in the always-on supply regulator. Besides having low power consumption, supply regulators for such IoT systems also need to have fast transient response to load current changes during a duty-cycled operation. Supply regulation using low quiescent current low dropout (LDO) regulators helps in extending the battery life of such power aware always-on applications with very long standby time. To serve as a supply regulator for such applications, a 1.24 µA quiescent current NMOS low dropout (LDO) is presented in this dissertation. This LDO uses a hybrid bias current generator (HBCG) to boost its bias current and improve the transient response. A scalable bias-current error amplifier with an on-demand buffer drives the NMOS pass device. The error amplifier is powered with an integrated dynamic frequency charge pump to ensure low dropout voltage. A low-power relaxation oscillator (LPRO) generates the charge pump clocks. Switched-capacitor pole tracking (SCPT) compensation scheme is proposed to ensure stability up to maximum load current of 150 mA for a low-ESR output capacitor range of 1 - 47µF. Designed in a 0.25 µm CMOS process, the LDO has an output voltage range of 1V – 3V, a dropout voltage of 240 mV, and a core area of 0.11 mm2.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

    FVF-Based Low-Dropout Voltage Regulator with Fast Charging/Discharging Paths for Fast Line and Load Regulation

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    A new internally compensated low drop-out voltage regulator based on the cascoded flipped voltage follower is presented in this paper. Adaptive biasing current and fast charging/discharging paths have been added to rapidly charge and discharge the parasitic capacitance of the pass transistor gate, thus improving the transient response. The proposed regulator was designed with standard 65-nm CMOS technology. Measurements show load and line regulations of 433.80 μV/mA and 5.61 mV/V, respectively. Furthermore, the output voltage spikes are kept under 76 mV for 0.1 mA to 100 mA load variations and 0.9 V to 1.2 V line variations with rise and fall times of 1 μs. The total current consumption is 17.88 μA (for a 0.9 V supply voltage).Ministerio de Economía y Competitividad TEC2015-71072-C3-3-RConsejería de Economía, Innovación y Ciencia. Junta de Andalucía P12-TIC-186

    Full On-chip low dropout voltage regulator with an enhanced transient response for low power systems

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    A full on chip low Dropout Voltage Regulator (LDO) with fast transient response and small capacitor compensation circuit is proposed. The novel technique is implemented to detect the variation voltage at the output of LDO and enable the proposed fast detector amplifier (FDA) to improve load transient response of 50mA load step. The large external capacitor used in Conventional LDO Regulators is removed allowing for greater power system integration for system-on-chip (SoC) applications. The 1.6-V Full On-Chip LDO voltage regulator with a power supply of 1.8 V was designed and simulated in the 0.18µm CMOS technology, consuming only 14 µA of ground current with a fast settling-time LNR(Line Regulation) and LOR(Load regulation) of 928ns and 883ns respectively while the rise and fall times in LNR and LOR is 500ns

    Design of low-dropout regulator for ultra low power on-chip applications

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    Low Drop Out (LDO) voltage regulators are commonly used to supply low-voltage digital circuits such as microprocessor cores. These digital circuits normally are continuously changing from one mode of operation to another. Therefore, the load demand can change rapidly resulting in large voltage transients at the output of the regulator which can adversely affect the digital circuitry. In this Master's Thesis, design topologies and challenges of very low-power fully integrated On-Chip Low-Dropout (LDO) regulators have been analyzed. Instead of conventional LDO which makes use of a large external capacitor to have better dynamic response and stability, a CapacitorLess LDO (CL-LDO) is chosen on considerations of smaller area. The most challenging part of designing this kind of regulator is achieving high current efficiency by reducing the quiescent current while ensuring good stability response as well as good regulation performance. Thus, different circuit techniques must be carefully added in order to balance the lack of the large external capacitor having the minimum impact on system efficiency. This work focuses on designing a fully integrated low-dropout regulator with good dynamic performance, high regulation performance and ultra-low power consumption. The stability is achieved by the use of two pole-splitting techniques, namely Cascode and Nested-Miller compensation. The good dynamic response with low quiescent current are achieved by the use of an adaptive biasing circuit, a gm-boost circuit and adaptive power transistor architecture

    Development of high-performance low-dropout regulators for SoC applications.

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    Or, Pui Ying."July 2010."Thesis (M.Phil.)--Chinese University of Hong Kong, 2010.Includes bibliographical references.Abstracts in English and Chinese.AcknowledgmentsTable of ContentList of FiguresList of TablesList of PublicationsChapter Chapter 1 - --- Background of LDO ResearchChapter 1.1 --- Structure of a LDO --- p.1-1Chapter 1.2 --- Principle of Operation of LDO --- p.1-2Chapter 1.3 --- Steady-State Specification of LDO --- p.1-3Chapter 1.4 --- High-Frequency Specification of LDO --- p.1-3Chapter 1.5 --- Dynamic Specification of LDO --- p.1-4Chapter 1.6 --- An Advanced LDO Structure --- p.1-4Chapter 1.7 --- Contribution and Outline of the Thesis --- p.1-5References --- p.1-6Chapter Chapter 2 - --- PSRR AnalysisChapter 2.1 --- Modeling of the PSRR of LDO --- p.2-3Chapter 2.2 --- Analysis of LDO Circuit Using Proposed Modeling --- p.2-6Chapter 2.3 --- Conclusion of Chapter --- p.2-12References --- p.2-13Chapter Chapter 3- --- An Output-Capacitorless LDO with Direct Voltage-Spike DetectionChapter 3.1 --- Analysis of Output-Capacitorless LDO --- p.3-5Chapter 3.2 --- LDO with Proposed Voltage-Spike Detection Circuit --- p.3-7Chapter 3.3 --- Experimental Results --- p.3-15Chapter 3.4 --- Conclusion of Chapter --- p.3-21References --- p.3-22Chapter Chapter 4 - --- A LDO with Impedance Adjustment and Loop-Gain Boosting TechniqueChapter 4.1 --- Proposed LDO --- p.4-3Chapter 4.2 --- Experimental Results --- p.4-7Chapter 4.3 --- Comparison --- p.4-11Chapter 4.4 --- Conclusion of Chapter --- p.4-12Reference --- p.4-13Chapter Chapter 5 - --- Conclusion and Future Wor

    Power Supply Rejection Improvement Techniques In Low Drop-Out Voltage Regulators

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    Low drop out (LDO) voltage regulators are widely used for post regulating the switching ripples generated by the switched mode power supplies (SMPS). Due to demand for portable applications, industry is pushing for complete system on chip power management solutions. Hence, the switching frequencies of the SMPS are increasing to allow higher level of integration. Therefore, the subsequent post-regulator LDO must have good power supply rejection (PSR) up to switching frequencies of SMPS. Unfortunately, the conventional LDOs have poor PSR at high frequencies. The objective of this research is to develop novel LDO regulators that can achieve good high frequency PSR performance. In this thesis, two PSR improvement methods are presented. The first method proposes a novel power supply noise-cancelling scheme to improve the PSR of an external-capacitor LDO. The proposed power supply noise-cancelling scheme is designed using adaptive power consumption, thereby not degrading the power efficiency of the LDO. The second method proposes a feed forward ripple cancellation technique to improve the PSR of capacitor-less LDO; also a dynamically powered transient improvement scheme has been proposed. The feed forward ripple cancellation is designed by reusing the load transient improvement block, thus achieving the improvement in PSR with no additional power consumption. Both the projects have been designed in TSMC 0.18 μm technology. The first method achieves a PSR of 66 dB up to 1 MHz where as the second method achieves a 55 dB PSR up to 1 MHz

    Low Power DC-DC Converters and a Low Quiescent Power High PSRR Class-D Audio Amplifier

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    High-performance DC-DC voltage converters and high-efficient class-D audio amplifiers are required to extend battery life and reduce cost in portable electronics. This dissertation focuses on new system architectures and design techniques to reduce area and minimize quiescent power while achieving high performance. Experimental results from prototype circuits to verify theory are shown. Firstly, basics on low drop-out (LDO) voltage regulators are provided. Demand for system-on-chip solutions has increased the interest in LDO voltage regulators that do not require a bulky off-chip capacitor to achieve stability, also called capacitor- less LDO (CL-LDO) regulators. Several architectures have been proposed; however, comparing these reported architectures proves difficult, as each has a distinct process technology and specifications. This dissertation compares CL-LDOs in a unified manner. Five CL-LDO regulator topologies were designed, fabricated, and tested under common design conditions. Secondly, fundamentals on DC-DC buck converters are presented and area reduction techniques for the external output filter, power stage, and compensator are proposed. A fully integrated buck converter using standard CMOS technology is presented. The external output filter has been fully-integrated by increasing the switching frequency up to 45 MHz. Moreover, a monolithic single-input dual-output buck converter is proposed. This architecture implements only three switches instead of the four switches used in conventional solutions, thus potentially reducing area in the power stage through proper design of the power switches. Lastly, a monolithic PWM voltage mode buck converter with compact Type-III compensation is proposed. This compensation scheme employs a combination of Gm-RC and Active-RC techniques to reduce the area of the compensator, while maintaining low quiescent power consumption and fast transient response. The proposed compensator reduces area by more than 45% when compared to an equivalent conventional Type-III compensator. Finally, basics on class-D audio amplifiers are presented and a clock-free current controlled class-D audio amplifier using integral sliding mode control is proposed. The proposed amplifier achieves up to 82 dB of power supply rejection ratio and a total harmonic distortion plus noise as low as 0.02%. The IC prototype’s controller consumes 30% less power than those featured in recently published works

    Power-Efficient and High-Performance Cicruit Techniques for On-Chip Voltage Regulation and Low-Voltage Filtering

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    This dissertation focuses on two projects. The first one is a power supply rejection (PSR) enhanced with fast settling time (TS) bulk-driven feedforward (BDFF) capacitor-less (CL) low-dropout (LDO) regulator. The second project is a high bandwidth (BW) power adjustable low-voltage (LV) active-RC 4th -order Butterworth low pass filter (LPF). As technology improves, faster and more accurate LDOs with high PSR are going to be required for future on-chip applications and systems.The proposed BDFF CL-LDO will accomplish an improved PSR without degrading TS. This would be achieved by injecting supply noise through the pass device’s bulk terminal in order to cancel the supply noise at the output. The supply injection will be achieved by creating a feedforward path, which compared to feedback paths, that doesn’t degrade stability and therefore allows for faster dynamic performance. A high gain control loop would be used to maintain a high accuracy and dc performance, such as line/load regulation. The proposed CL-LDO will target a PSR better than – 90 dB at low frequencies and – 60 dB at 1 MHz for 50 mA of load current (IvL). The CL-LDO will target a loop gain higher than 90 dB, leading to an improved line and load regulation, and unity-gain frequency (UGF) higher than 20 MHz, which will allow a TS faster than 500 ns. The CL-LDO is going to be fabricated in a CMOS 130 nm technology; consume a quiescent current (IQ) of less than 50 μA; for a dropout voltage of 200 mV and an IvL of 50 mA. As technology scales down, speed and performance requirements increase for on-chip communication systems that reflect the current demand for high speed data-oriented applications. However, in small technologies, it becomes harder to achieve high gain and high speed at the same time because the supply voltage (VvDvD) decreases leaving no room for conventional high gain CMOS structures. The proposed active-RC LPF will accomplish a LV high BW operation that would allow such disadvantages to be overcome. The LPF will be implemented using an active RC structure that allows for the high linearity such communication systems demand. In addition, built-in BW and power configurability would address the demands for increased flexibility usually required in such systems. The proposed LV LPF will target a configurable cut-off frequency (ƒо) of 20/40/80/160 MHz with tuning capabilities and power adjustability for each ƒо. The filter will be fabricated in a CMOS 130 nm technology. The filter characteristics are as following: 4th -order, active-RC, LPF, Butterworth response, VDD = 0.6 V, THD higher than 40 dB and a third-order input intercept point (IIP3) higher than 10 dBm
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