10,798 research outputs found

    Run-time resource management in fault-tolerant network on reconfigurable chips

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    Applied constant gain amplification in circulating loop experiments

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    The reconfiguration of channel or wavelength routes in optically transparent mesh networks can lead to deviations in channel power that may impact transmission performance. A new experimental approach, applied constant gain, is used to maintain constant gain in a circulating loop enabling the study of gain error effects on long-haul transmission under reconfigured channel loading. Using this technique we examine a number of channel configurations and system tuning operations for both full-span dispersion-compensated and optimized dispersion-managed systems. For each system design, large power divergence was observed with a maximum of 15 dB at 2240 km, when switching was implemented without additional system tuning. For a bit error rate of 10-3, the maximum number of loop circulations was reduced by up to 33%

    Cycle-accurate evaluation of reconfigurable photonic networks-on-chip

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    There is little doubt that the most important limiting factors of the performance of next-generation Chip Multiprocessors (CMPs) will be the power efficiency and the available communication speed between cores. Photonic Networks-on-Chip (NoCs) have been suggested as a viable route to relieve the off- and on-chip interconnection bottleneck. Low-loss integrated optical waveguides can transport very high-speed data signals over longer distances as compared to on-chip electrical signaling. In addition, with the development of silicon microrings, photonic switches can be integrated to route signals in a data-transparent way. Although several photonic NoC proposals exist, their use is often limited to the communication of large data messages due to a relatively long set-up time of the photonic channels. In this work, we evaluate a reconfigurable photonic NoC in which the topology is adapted automatically (on a microsecond scale) to the evolving traffic situation by use of silicon microrings. To evaluate this system's performance, the proposed architecture has been implemented in a detailed full-system cycle-accurate simulator which is capable of generating realistic workloads and traffic patterns. In addition, a model was developed to estimate the power consumption of the full interconnection network which was compared with other photonic and electrical NoC solutions. We find that our proposed network architecture significantly lowers the average memory access latency (35% reduction) while only generating a modest increase in power consumption (20%), compared to a conventional concentrated mesh electrical signaling approach. When comparing our solution to high-speed circuit-switched photonic NoCs, long photonic channel set-up times can be tolerated which makes our approach directly applicable to current shared-memory CMPs

    Dynamic circulating-loop methods for transmission experiments in optically transparent networks

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    Recent experiments incorporating multiple fast switching elements and automated system configuration in a circulating loop apparatus have enabled the study of aspects of long-haul WDM transmission unique to optically transparent networks. Techniques include per-span switching to measure the performance limits due to dispersion compensation granularity and mesh network walk-off, and applied constant-gain amplification to evaluate wavelength reconfiguration penalties

    Coarse-grained reconfigurable array architectures

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    Coarse-Grained Reconfigurable Array (CGRA) architectures accelerate the same inner loops that benefit from the high ILP support in VLIW architectures. By executing non-loop code on other cores, however, CGRAs can focus on such loops to execute them more efficiently. This chapter discusses the basic principles of CGRAs, and the wide range of design options available to a CGRA designer, covering a large number of existing CGRA designs. The impact of different options on flexibility, performance, and power-efficiency is discussed, as well as the need for compiler support. The ADRES CGRA design template is studied in more detail as a use case to illustrate the need for design space exploration, for compiler support and for the manual fine-tuning of source code

    Reconfigurable Flood Wall Inspired by Architected Origami

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    Recent interest in the art of origami has opened a wide range of engineering applications and possibilities. Shape changing structures based on origami have had a large influence on the drive for efficient, sustainable engineering solutions. However, development in novel macro-scale utilization is lacking compared to the effort towards micro-scale devices. There exists an opening for environmentally actuated structures that improve quality for life of humans and the natural environment. Specifically, resilient infrastructure systems could potentially benefit from the tailorable properties and programmable reconfiguration of origami-inspired designs. The realm of flood protection and overall water resources management creates a unique opportunity for adaptable structures. A flood protection system, or flood wall, is one application of the origami technique. In many situations, flood protection is visually displeasing and hinders an otherwise scenic natural environment within a cityscape. By applying a permanent, adaptable protection system in flood-prone areas, not only will general aesthetics be conserved, but quick deployment in disaster situations will be ensured. With a rapidly changing climate and an increase in storm disaster events, an efficient flood-protection system is vital. In this study, simple rigid flood barriers are compared to adaptable wall systems that utilize multi-stable configurations. The flood event is characterized by a surcharge of water that is suddenly introduced–like that of a flash flood–and sustained at steady-state. Small-scale prototypes are tested in a hydraulic flume and compared to a numerical simulation for validation.Ohio State University College of Engineering Undergraduate Research ScholarshipNo embargoAcademic Major: Civil Engineerin
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