On thermal sensor calibration and software techniques for many-core thermal management

The high power density of a many-core processor results in increased temperature which negatively impacts system reliability and performance. Dynamic thermal management applies thermal-aware techniques at run time to avoid overheating using temperature information collected from on-chip thermal sensors. Temperature sensing and thermal control schemes are two critical technologies for successfully maintaining thermal safety. In this dissertation, on-line thermal sensor calibration schemes are developed to provide accurate temperature information. Software-based dynamic thermal management techniques are proposed using calibrated thermal sensors. Due to process variation and silicon aging, on-chip thermal sensors require periodic calibration before use in DTM. However, the calibration cost for thermal sensors can be prohibitively high as the number of on-chip sensors increases. Linear models which are suitable for on-line calculation are employed to estimate temperatures at multiple sensor locations using performance counters. The estimated temperature and the actual sensor thermal profile show a very high similarity with correlation coefficient ~0.9 for SPLASH2 and SPEC2000 benchmarks. A calibration approach is proposed to combine potentially inaccurate temperature values obtained from two sources: thermal sensor readings and temperature estimations. A data fusion strategy based on Bayesian inference, which combines information from these two sources, is demonstrated. The result shows the strategy can effectively recalibrate sensor readings in response to inaccuracies caused by process variation and environmental noise. The average absolute error of the corrected sensor temperature readings is A dynamic task allocation strategy is proposed to address localized overheating in many-core systems. Our approach employs reinforcement learning, a dynamic machine learning algorithm that performs task allocation based on current temperatures and a prediction regarding which assignment will minimize the peak temperature. Our results show that the proposed technique is fast (scheduling performed in \u3c1 \u3ems) and can efficiently reduce peak temperature by up to 8 degree C in a 49-core processor (6% on average) versus a leading competing task allocation approach for a series of SPLASH-2 benchmarks. Reinforcement learning has also been applied to 3D integrated circuits to allocate tasks with thermal awareness

Characterization of new hybrid pixel module concepts for the ATLAS Insertable B-Layer upgrade

The ATLAS Insertable B-Layer (IBL) collaboration plans to insert a fourth pixel layer inside the present Pixel Detector to recover from eventual failures in the current pixel system, especially the b-layer. Additionally the IBL will ensure excellent tracking, vertexing and b-tagging performance during the LHC phase I and add robustness in tracking with high luminosity pile-up. The expected peak luminosity for IBL is 2 to 3centerdot1034 cm-2s-1 and IBL is designed for an integrated luminosity of 700 fb-1. This corresponds to an expected fluence of 5centerdot1015 1 MeV neqcm-2 and a total ionizing dose of 250 MRad. In order to cope with these requirements, two new module concepts are under investigation, both based on a new front end IC, called FE-I4. This IC was designed as readout chip for future ATLAS Pixel Detectors and its first application will be the IBL. The planar pixel sensor (PPS) based module concept benefits from its well understood design, which is kept as similar as possible to the design of the current ATLAS Pixel Detector sensor. The second approach of the new three dimensional (3D) silicon sensor technology benefits from the shorter charge carrier drift distance to the electrodes, which completely penetrate the sensor bulk. Prototype modules of both sensor concepts have been build and tested in laboratory and test beam environment before and after irradiation. Both concepts show very high performance even after irradiation to 5centerdot1015 1 MeV neqcm-2 and meet the IBL specifications in terms of hit efficiency being larger than 97%. Lowest operational threshold studies have been effected and prove independent of the used sensor concept the excellent performance of FE-I4 based module concepts in terms of noise hit occupancy at low thresholds.Comment: Part of 9th International Conference on Position Sensitive Detectors (PSD9

Fine-grained Energy and Thermal Management using Real-time Power Sensors

With extensive use of battery powered devices such as smartphones, laptops an

Characterisation of the Medipix3 detector for 60 and 80 keV electrons

In this paper we report quantitative measurements of the imaging performance for the current generation of hybrid pixel detector, Medipix3, used as a direct electron detector. We have measured the modulation transfer function and detective quantum efficiency at beam energies of 60 and 80 keV. In single pixel mode, energy threshold values can be chosen to maximize either the modulation transfer function or the detective quantum efficiency, obtaining values near to, or exceeding those for a theoretical detector with square pixels. The Medipix3 charge summing mode delivers simultaneous, high values of both modulation transfer function and detective quantum efficiency. We have also characterized the detector response to single electron events and describe an empirical model that predicts the detector modulation transfer function and detective quantum efficiency based on energy threshold. Exemplifying our findings we demonstrate the Medipix3 imaging performance recording a fully exposed electron diffraction pattern at 24-bit depth together with images in single pixel and charge summing modes. Our findings highlight that for transmission electron microscopy performed at low energies (energies <100 keV) thick hybrid pixel detectors provide an advantageous architecture for direct electron imaging

Design and development of auxiliary components for a new two-stroke, stratified-charge, lean-burn gasoline engine

A unique stepped-piston engine was developed by a group of research engineers at Universiti Teknologi Malaysia (UTM), from 2003 to 2005. The development work undertaken by them engulfs design, prototyping and evaluation over a predetermined period of time which was iterative and challenging in nature. The main objective of the program is to demonstrate local R&D capabilities on small engine work that is able to produce mobile powerhouse of comparable output, having low-fuel consumption and acceptable emission than its crankcase counterpart of similar displacement. A two-stroke engine work was selected as it posses a number of technological challenges, increase in its thermal efficiency, which upon successful undertakings will be useful in assisting the group in future powertrain undertakings in UTM. In its carbureted version, the single-cylinder aircooled engine incorporates a three-port transfer system and a dedicated crankcase breather. These features will enable the prototype to have high induction efficiency and to behave very much a two-stroke engine but equipped with a four-stroke crankcase lubrication system. After a series of analytical work the engine was subjected to a series of laboratory trials. It was also tested on a small watercraft platform with promising indication of its flexibility of use as a prime mover in mobile platform. In an effort to further enhance its technology features, the researchers have also embarked on the development of an add-on auxiliary system. The system comprises of an engine control unit (ECU), a directinjector unit, a dedicated lubricant dispenser unit and an embedded common rail fuel unit. This support system was incorporated onto the engine to demonstrate the finer points of environmental-friendly and fuel economy features. The outcome of this complete package is described in the report, covering the methodology and the final characteristics of the mobile power plant

Modeling the Temperature Bias of Power Consumption for Nanometer-Scale CPUs in Application Processors

We introduce and experimentally validate a new macro-level model of the CPU temperature/power relationship within nanometer-scale application processors or system-on-chips. By adopting a holistic view, this model is able to take into account many of the physical effects that occur within such systems. Together with two algorithms described in the paper, our results can be used, for instance by engineers designing power or thermal management units, to cancel the temperature-induced bias on power measurements. This will help them gather temperature-neutral power data while running multiple instance of their benchmarks. Also power requirements and system failure rates can be decreased by controlling the CPU's thermal behavior. Even though it is usually assumed that the temperature/power relationship is exponentially related, there is however a lack of publicly available physical temperature/power measurements to back up this assumption, something our paper corrects. Via measurements on two pertinent platforms sporting nanometer-scale application processors, we show that the power/temperature relationship is indeed very likely exponential over a 20{\deg}C to 85{\deg}C temperature range. Our data suggest that, for application processors operating between 20{\deg}C and 50{\deg}C, a quadratic model is still accurate and a linear approximation is acceptable.Comment: Submitted to SAMOS 2014; International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV