A Multi-objective Perspective for Operator Scheduling using Fine-grained DVS Architecture

The stringent power budget of fine grained power managed digital integrated circuits have driven chip designers to optimize power at the cost of area and delay, which were the traditional cost criteria for circuit optimization. The emerging scenario motivates us to revisit the classical operator scheduling problem under the availability of DVFS enabled functional units that can trade-off cycles with power. We study the design space defined due to this trade-off and present a branch-and-bound(B/B) algorithm to explore this state space and report the pareto-optimal front with respect to area and power. The scheduling also aims at maximum resource sharing and is able to attain sufficient area and power gains for complex benchmarks when timing constraints are relaxed by sufficient amount. Experimental results show that the algorithm that operates without any user constraint(area/power) is able to solve the problem for most available benchmarks, and the use of power budget or area budget constraints leads to significant performance gain.Comment: 18 pages, 6 figures, International journal of VLSI design & Communication Systems (VLSICS

Neural reactivations during sleep determine network credit assignment.

A fundamental goal of motor learning is to establish the neural patterns that produce a desired behavioral outcome. It remains unclear how and when the nervous system solves this 'credit assignment' problem. Using neuroprosthetic learning, in which we could control the causal relationship between neurons and behavior, we found that sleep-dependent processing was required for credit assignment and the establishment of task-related functional connectivity reflecting the casual neuron-behavior relationship. Notably, we observed a strong link between the microstructure of sleep reactivations and credit assignment, with downscaling of non-causal activity. Decoupling of spiking to slow oscillations using optogenetic methods eliminated rescaling. Thus, our results suggest that coordinated firing during sleep is essential for establishing sparse activation patterns that reflect the causal neuron-behavior relationship

Dynamic Tensor Clustering

Dynamic tensor data are becoming prevalent in numerous applications. Existing tensor clustering methods either fail to account for the dynamic nature of the data, or are inapplicable to a general-order tensor. Also there is often a gap between statistical guarantee and computational efficiency for existing tensor clustering solutions. In this article, we aim to bridge this gap by proposing a new dynamic tensor clustering method, which takes into account both sparsity and fusion structures, and enjoys strong statistical guarantees as well as high computational efficiency. Our proposal is based upon a new structured tensor factorization that encourages both sparsity and smoothness in parameters along the specified tensor modes. Computationally, we develop a highly efficient optimization algorithm that benefits from substantial dimension reduction. In theory, we first establish a non-asymptotic error bound for the estimator from the structured tensor factorization. Built upon this error bound, we then derive the rate of convergence of the estimated cluster centers, and show that the estimated clusters recover the true cluster structures with a high probability. Moreover, our proposed method can be naturally extended to co-clustering of multiple modes of the tensor data. The efficacy of our approach is illustrated via simulations and a brain dynamic functional connectivity analysis from an Autism spectrum disorder study.Comment: Accepted at Journal of the American Statistical Associatio

A functional link network based adaptive power system stabilizer

An on-line identifier using Functional Link Network (FLN) and Pole-shift (PS) controller for power system stabilizer (PSS) application are presented in this thesis. To have the satisfactory performance of the PSS controller, over a wide range of operating conditions, it is desirable to adapt PSS parameters in real time. Artificial Neural Networks (ANNs) transform the inputs in a low-dimensional space to high-dimensional nonlinear hidden unit space and they have the ability to model the nonlinear characteristics of the power system. The ability of ANNs to learn makes them more suitable for use in adaptive control techniques. On-line identification obtains a mathematical model at each sampling period to track the dynamic behavior of the plant. The ANN identifier consisting of a Functional link Network (FLN) is used for identifying the model parameters. A FLN model eliminates the need of hidden layer while retaining the nonlinear mapping capability of the neural network by using enhanced inputs. This network may be conveniently used for function approximation with faster convergence rate and lesser computational load. The most commonly used Pole Assignment (PA) algorithm for adaptive control purposes assign the pole locations to fixed locations within the unit circle in the z-plane. It may not be optimum for different operating conditions. In this thesis, PS type of adaptive control algorithm is used. This algorithm, instead of assigning the closed-loop poles to fixed locations within the unit circle in the z-plane, this algorithm assumes that the pole characteristic polynomial of the closed-loop system has the same form as the pole characteristic of the open-loop system and shifts the open-loop poles radially towards the centre of the unit circle in the z-plane by a shifting factor α according to some rules. In this control algorithm, no coefficients need to be tuned manually, so manual parameter tuning (which is a drawback in conventional power system stabilizer) is minimized. The PS control algorithm uses the on-line updated ARMA parameters to calculate the new closed-loop poles of the system that are always inside the unit circle in the z-plane. Simulation studies on a single-machine infinite bus and on a multi-machine power system for various operating condition changes, verify the effectiveness of the combined model of FLN identifier and PS control in damping the local and multi-mode oscillations occurring in the system. Simulation studies prove that the APSSs have significant benefits over conventional PSSs: performance improvement and no requirement for parameter tuning

DISCUS: the distributed core for ubiquitous broadband access

A new end to end architecture based on Long-Reach Passive Optical Network (LR-PON) with wireless integration, a distributed core built of optical transparency islands and an OpenFlow-based control plane, which is being developed in the EU project DISCUS, is described in this paper. The main technological advances and the network modelling and optimization approach are reported

Flexible compiler-managed L0 buffers for clustered VLIW processors

Wire delays are a major concern for current and forthcoming processors. One approach to attack this problem is to divide the processor into semi-independent units referred to as clusters. A cluster usually consists of a local register file and a subset of the functional units, while the data cache remains centralized. However, as technology evolves, the latency of such a centralized cache increase leading to an important performance impact. In this paper, we propose to include flexible low-latency buffers in each cluster in order to reduce the performance impact of higher cache latencies. The reduced number of entries in each buffer permits the design of flexible ways to map data from L1 to these buffers. The proposed L0 buffers are managed by the compiler, which is responsible to decide which memory instructions make us of them. Effective instruction scheduling techniques are proposed to generate code that exploits these buffers. Results for the Mediabench benchmark suite show that the performance of a clustered VLIW processor with a unified L1 data cache is improved by 16% when such buffers are used. In addition, the proposed architecture also shows significant advantages over both MultiVLIW processors and clustered processors with a word-interleaved cache, two state-of-the-art designs with a distributed L1 data cache.Peer ReviewedPostprint (published version