272,025 research outputs found

    A dynamic power-aware partitioner with task migration for multicore embedded systems

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    Nowadays, a key design issue in embedded systems is how to reduce the power consumption, since batteries have a limited energy budget. For this purpose, several techniques such as Dynamic Voltage Scaling (DVS) or task migration can be used. DVS allows reducing power by selecting the optimal voltage supply, while task migration achieves this effect by balancing the workload among cores. This paper first analyzes the impact on energy due to task migration in multicore embedded systems with DVS capability and using the well-known Worst Fit (WF) partitioning heuristic. To reduce overhead, migrations are only performed at the time that a task arrives to and/or leaves the system and, in such a case, only one migration is allowed. The huge potential on energy saving due to task migration, leads us to propose a new dynamic partitioner, namely DP, that migrates tasks in a more efficient way than typical partitioners. Unlike WF, the proposed algorithm examines which is the optimal target core before allowing a migration. Experimental results show that DP can improve energy consumption in a factor up to 2.74 over the typical WF algorithm. © 2011 Springer-Verlag.This work was supported by Spanish CICYT under Grant TIN2009-14475-C04-01, and by Consolider-Ingenio under Grant CSD2006-00046.March Cabrelles, JL.; Sahuquillo BorrĂĄs, J.; Petit MartĂ­, SV.; Hassan Mohamed, H.; Duato MarĂ­n, JF. (2011). A dynamic power-aware partitioner with task migration for multicore embedded systems. En Euro-Par 2011 Parallel Processing. Springer Verlag (Germany). 2011(6852):218-229. https://doi.org/10.1007/978-3-642-23400-2_21S21822920116852AlEnawy, T.A., Aydin, H.: Energy-Aware Task Allocation for Rate Monotonic Scheduling. In: Proceedings of the 11th Real Time on Embedded Technology and Applications Symposium, March 7-10, pp. 213–223. IEEE Computer Society, San Francisco (2005)Aydin, H., Yang, Q.: Energy-Aware Partitioning for Multiprocessor Real-Time Systems. In: Proceedings of the 17th International Parallel and Distributed Processing Symposium, Workshop on Parallel and Distributed Real-Time Systems, April 22-26, p. 113. IEEE Computer Society, Nice (2003)Baker, T.P.: An Analysis of EDF schedulability on a multiprocessor. IEEE Transactions on Parallel and Distributed Systems 16(8), 760–768 (2005)Brandenburg, B.B., Calandrino, J.M., Anderson, J.H.: On the Scalability of Real-Time Scheduling Algorithms on Multicore Platforms: A Case Study. In: Proceedings of the 29th Real-Time Systems Symposium, November 30-December 3, pp. 157–169. IEEE Computer Society, Barcelona (2008)BriĂŁo, E., Barcelos, D., Wronski, F., Wagner, F.R.: Impact of Task Migration in NoC-based MPSoCs for Soft Real-time Applications. In: Proceedings of the International Conference on VLSI, October 15-17, pp. 296–299. IEEE Computer Society, Atlanta (2007)Cazorla, F., Knijnenburg, P., Sakellariou, R., FernĂĄndez, E., Ramirez, A., Valero, M.: Predictable Performance in SMT Processors: Synergy between the OS and SMTs. IEEE Transactions on Computers 55(7), 785–799 (2006)Donald, J., Martonosi, M.: Techniques for Multicore Thermal Management: Classification and New Exploration. In: Proceedings of the 33rd Annual International Symposium on Computer Architecture, June 17-21, pp. 78–88. IEEE Computer Society, Boston (2006)El-Haj-Mahmoud, A., AL-Zawawi, A., Anantaraman, A., Rotenberg, E.: Virtual Multiprocessor: An Analyzable, High-Performance Architecture for Real-Time Computing. In: Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, September 24-27, pp. 213–224. ACM Press, San Francisco (2005)Hung, C., Chen, J., Kuo, T.: Energy-Efficient Real-Time Task Scheduling for a DVS System with a Non-DVS Processing Element. In: Proceedings of the 27th Real-Time Systems Symposium, December 5-8, pp. 303–312. IEEE Computer Society, Rio de Janeiro (2006)Kalla, R., Sinharoy, B., Tendler, J.M.: IBM Power5 Chip: A Dual-Core Multithreaded Processor. IEEE Micro 24(2), 40–47 (2004)Kato, S., Yamasaki, N.: Global EDF-based Scheduling with Efficient Priority Promotion. In: Proceedings of the 14th International Conference on Embedded and Real-Time Computing Systems and Applications, August 25-27, pp. 197–206. IEEE Computer Society, Kaohisung (2008)Malardalen Real-Time Research Center, Vasteras, Sweden: WCET Analysis Project. WCET Benchmark Programs (2006), [Online], http://www.mrtc.mdh.se/projects/wcet/March, J., Sahuquillo, J., Hassan, H., Petit, S., Duato, J.: A New Energy-Aware Dynamic Task Set Partitioning Algorithm for Soft and Hard Embedded Real-Time Systems. To be published on The Computer Journal (2011)McNairy, C., Bhatia, R.: Montecito: A Dual-Core, Dual-Thread Itanium Processor. IEEE Micro 25(2), 10–20 (2005)Seo, E., Jeong, J., Park, S., Lee, J.: Energy Efficient Scheduling of Real-Time Tasks on Multicore Processors. IEEE Transactions on Parallel and Distributed Systems 19(11), 1540–1552 (2008)Shah, A.: Arm plans to add multithreading to chip design. ITworld (2010), [Online], http://www.itworld.com/hardware/122383/arm-plans-add-multithreading-chip-designUbal, R., Sahuquillo, J., Petit, S., LĂłpez, P.: Multi2Sim: A Simulation Framework to Evaluate Multicore-Multithreaded Processors. In: Proceedings of the 19th International Symposium on Computer Architecture and High Performance Computing, October 24-27, pp. 62–68. IEEE Computer Society, Gramado (2007)Watanabe, R., Kondo, M., Imai, M., Nakamura, H., Nanya, T.: Task Scheduling under Performance Constraints for Reducing the Energy Consumption of the GALS Multi-Processor SoC. In: Proceedings of the Design Automation and Test in Europe, April 16-20, pp. 797–802. ACM, Nice (2007)Wei, Y., Yang, C., Kuo, T., Hung, S.: Energy-Efficient Real-Time Scheduling of Multimedia Tasks on Multi-Core Processors. In: Proceedings of the 25th Symposium on Applied Computing, March 22-26, pp. 258–262. ACM, Sierre (2010)Wu, Q., Martonosi, M., Clark, D.W., Reddi, V.J., Connors, D., Wu, Y., Lee, J., Brooks, D.: A Dynamic Compilation Framework for Controlling Microprocessor Energy and Performance. In: Proceedings of the 38th Annual IEEE/ACM International Symposium on Microarchitecture, November 12-16, pp. 271–282. IEEE Computer Society, Barcelona (2005)Zheng, L.: A Task Migration Constrained Energy-Efficient Scheduling Algorithm for Multiprocessor Real-time Systems. In: Proceedings of the International Conference on Wireless Communications, Networking and Mobile Computing, September 21-25, pp. 3055–3058. IEEE Computer Society, Shanghai (2007

    GT2007-27862 REAL-TIME HEALTH ESTIMATION AND AUTOMATED FAULT ACCOMMODATION FOR PROPULSION SYSTEMS

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    ABSTRACT This paper presents the development of innovative realtime health estimation and automated fault accommodation techniques for advanced propulsion systems within a Dynamic Decision Support (D 2 S) framework. The proposed approach uses dynamic models in a real-time computing environment to not only diagnose system degradation and faults, but also to determine "on the fly" how to accommodate for them. The realtime health estimation modules enhance on-board PHM (Prognosis & Health Management) capabilities with a dynamic system identification algorithm that is capable of detecting faults with a continuously updated dynamic model. In addition, a real-time, self-tuning Kalman filter and fault classification algorithm are combined to provide accurate health estimation. Based on the inferred health condition, mission requirements and flight regime information, the automated fault accommodation module automatically makes decisions regarding control reconfiguration and change of control strategies. The presented techniques have been applied to a generic turbofan engine model with simulated engine component faults and degradation and simulation results are presented. To further raise the technological readiness level, select algorithms have been implemented and evaluated on a PC104 embedded platform. The dynamic modeling capabilities, techniques and tools sets will not only improve the reliability of the propulsion systems, but also greatly enhance maintenance decision support and contingency planning concepts

    Contract Aware Components, 10 years after

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    The notion of contract aware components has been published roughly ten years ago and is now becoming mainstream in several fields where the usage of software components is seen as critical. The goal of this paper is to survey domains such as Embedded Systems or Service Oriented Architecture where the notion of contract aware components has been influential. For each of these domains we briefly describe what has been done with this idea and we discuss the remaining challenges.Comment: In Proceedings WCSI 2010, arXiv:1010.233

    A Survey of Techniques For Improving Energy Efficiency in Embedded Computing Systems

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    Recent technological advances have greatly improved the performance and features of embedded systems. With the number of just mobile devices now reaching nearly equal to the population of earth, embedded systems have truly become ubiquitous. These trends, however, have also made the task of managing their power consumption extremely challenging. In recent years, several techniques have been proposed to address this issue. In this paper, we survey the techniques for managing power consumption of embedded systems. We discuss the need of power management and provide a classification of the techniques on several important parameters to highlight their similarities and differences. This paper is intended to help the researchers and application-developers in gaining insights into the working of power management techniques and designing even more efficient high-performance embedded systems of tomorrow

    Comparative Evaluation of Packet Classification Algorithms for Implementation on Resource Constrained Systems

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    This paper provides a comparative evaluation of a number of known classification algorithms that have been considered for both software and hardware implementation. Differently from other sources, the comparison has been carried out on implementations based on the same principles and design choices. Performance measurements are obtained by feeding the implemented classifiers with various traffic traces in the same test scenario. The comparison also takes into account implementation feasibility of the considered algorithms in resource constrained systems (e.g. embedded processors on special purpose network platforms). In particular, the comparison focuses on achieving a good compromise between performance, memory usage, flexibility and code portability to different target platforms

    A Survey of Prediction and Classification Techniques in Multicore Processor Systems

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    In multicore processor systems, being able to accurately predict the future provides new optimization opportunities, which otherwise could not be exploited. For example, an oracle able to predict a certain application\u27s behavior running on a smart phone could direct the power manager to switch to appropriate dynamic voltage and frequency scaling modes that would guarantee minimum levels of desired performance while saving energy consumption and thereby prolonging battery life. Using predictions enables systems to become proactive rather than continue to operate in a reactive manner. This prediction-based proactive approach has become increasingly popular in the design and optimization of integrated circuits and of multicore processor systems. Prediction transforms from simple forecasting to sophisticated machine learning based prediction and classification that learns from existing data, employs data mining, and predicts future behavior. This can be exploited by novel optimization techniques that can span across all layers of the computing stack. In this survey paper, we present a discussion of the most popular techniques on prediction and classification in the general context of computing systems with emphasis on multicore processors. The paper is far from comprehensive, but, it will help the reader interested in employing prediction in optimization of multicore processor systems

    FPGA-based Anomalous trajectory detection using SOFM

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    A system for automatically classifying the trajectory of a moving object in a scene as usual or suspicious is presented. The system uses an unsupervised neural network (Self Organising Feature Map) fully implemented on a reconfigurable hardware architecture (Field Programmable Gate Array) to cluster trajectories acquired over a period, in order to detect novel ones. First order motion information, including first order moving average smoothing, is generated from the 2D image coordinates (trajectories). The classification is dynamic and achieved in real-time. The dynamic classifier is achieved using a SOFM and a probabilistic model. Experimental results show less than 15\% classification error, showing the robustness of our approach over others in literature and the speed-up over the use of conventional microprocessor as compared to the use of an off-the-shelf FPGA prototyping board

    Methods of Technical Prognostics Applicable to Embedded Systems

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    HlavnĂ­ cĂ­lem dizertace je poskytnutĂ­ ucelenĂ©ho pohledu na problematiku technickĂ© prognostiky, kterĂĄ nachĂĄzĂ­ uplatněnĂ­ v tzv. prediktivnĂ­ ĂșdrĆŸbě zaloĆŸenĂ© na trvalĂ©m monitorovĂĄnĂ­ zaƙízenĂ­ a odhadu Ășrovně degradace systĂ©mu či jeho zbĂœvajĂ­cĂ­ ĆŸivotnosti a to zejmĂ©na v oblasti komplexnĂ­ch zaƙízenĂ­ a strojĆŻ. V současnosti je technickĂĄ diagnostika poměrně dobƙe zmapovanĂĄ a reĂĄlně nasazenĂĄ na rozdĂ­l od technickĂ© prognostiky, kterĂĄ je stĂĄle rozvĂ­jejĂ­cĂ­m se oborem, kterĂœ ovĆĄem postrĂĄdĂĄ větĆĄĂ­ mnoĆŸstvĂ­ reĂĄlnĂœch aplikaci a navĂ­c ne vĆĄechny metody jsou dostatečně pƙesnĂ© a aplikovatelnĂ© pro embedded systĂ©my. DizertačnĂ­ prĂĄce pƙinĂĄĆĄĂ­ pƙehled zĂĄkladnĂ­ch metod pouĆŸitelnĂœch pro Ășčely predikce zbĂœvajĂ­cĂ­ uĆŸitnĂ© ĆŸivotnosti, jsou zde popsĂĄny metriky pomocĂ­, kterĂœch je moĆŸnĂ© jednotlivĂ© pƙístupy porovnĂĄvat aĆ„ uĆŸ z pohledu pƙesnosti, ale takĂ© i z pohledu vĂœpočetnĂ­ nĂĄročnosti. Jedno z dizertačnĂ­ch jader tvoƙí doporučenĂ­ a postup pro vĂœběr vhodnĂ© prognostickĂ© metody s ohledem na prognostickĂĄ kritĂ©ria. DalĆĄĂ­m dizertačnĂ­m jĂĄdrem je pƙedstavenĂ­ tzv. částicovĂ©ho filtrovanĂ­ (particle filtering) vhodnĂ© pro model-based prognostiku s ověƙenĂ­m jejich implementace a porovnĂĄnĂ­m. HlavnĂ­ dizertačnĂ­ jĂĄdro reprezentuje pƙípadovou studii pro velmi aktuĂĄlnĂ­ tĂ©ma prognostiky Li-Ion baterii s ohledem na trvalĂ© monitorovĂĄnĂ­. PƙípadovĂĄ studie demonstruje proces prognostiky zaloĆŸenĂ© na modelu a srovnĂĄvĂĄ moĆŸnĂ© pƙístupy jednak pro odhad doby pƙed vybitĂ­m baterie, ale takĂ© sleduje moĆŸnĂ© vlivy na degradaci baterie. SoučástĂ­ prĂĄce je zĂĄkladnĂ­ ověƙenĂ­ modelu Li-Ion baterie a nĂĄvrh prognostickĂ©ho procesu.The main aim of the thesis is to provide a comprehensive overview of technical prognosis, which is applied in the condition based maintenance, based on continuous device monitoring and remaining useful life estimation, especially in the field of complex equipment and machinery. Nowadays technical prognosis is still evolving discipline with limited number of real applications and is not so well developed as technical diagnostics, which is fairly well mapped and deployed in real systems. Thesis provides an overview of basic methods applicable for prediction of remaining useful life, metrics, which can help to compare the different approaches both in terms of accuracy and in terms of computational/deployment cost. One of the research cores consists of recommendations and guide for selecting the appropriate forecasting method with regard to the prognostic criteria. Second thesis research core provides description and applicability of particle filtering framework suitable for model-based forecasting. Verification of their implementation and comparison is provided. The main research topic of the thesis provides a case study for a very actual Li-Ion battery health monitoring and prognostics with respect to continuous monitoring. The case study demonstrates the prognostic process based on the model and compares the possible approaches for estimating both the runtime and capacity fade. Proposed methodology is verified on real measured data.
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